DEC Digital Alpha VME 4/224 User Manual

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Digital Alpha VME 4/224 and

4/288 Single-Board Computers

User Guide and Technical Description

Order Number: EK–DAVME–TD. B01

This manual describes the Digital Alpha VME 4 module. It provides

conﬁguration and installation procedures and describes the module's

built-in features, including the console code and diagnostics.

Revision/Update Information:

Digital Equipment Corporation

Maynard, Massachusetts

This manual supersedes the Digital

Alpha VME 4/224 and 4/288

Single-Board Computers User

Guide and Technical Description,

EK–DAVME–TD. A01.

Table of Contents

Troubleshooting

Summary of Contents for DEC Digital Alpha VME 4/224

Page 1 Digital Alpha VME 4/224 and 4/288 Single-Board Computers User Guide and Technical Description Order Number: EK–DAVME–TD. B01 This manual describes the Digital Alpha VME 4 module. It provides conﬁguration and installation procedures and describes the module’s built-in features, including the console code and diagnostics.
Page 2 First Printing, July 1996 Revised, September 1996 Printed in U.S.A. The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. FCC Notice: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules.
Page 3: Table Of Contents
Contents Preface ..........1 Product Overview Product Description .
Page 4 3 Operating the Digital Alpha VME 4 Computer Controls and Indicators ......3–1 Console Mode ........3–3 3.2.1 Entering Console Mode .
Page 5 5 System Address Mapping CPU Address Mapping to PCI Space ....5–1 5.1.1 Cacheable Memory Space (0x000000000 to 0x0FFFFFFFF) ......5–4 Noncacheable Memory Space (0x100000000 to 5.1.2...
Page 6 Address Space of Control/Status Registers ... . . 6–8 Description of CSRs ......6–11 General Control Register .
Page 7 7.3.8 PCI Master Timeout ......7–7 7.3.9 Address Stepping in Conﬁguration Cycles ..7–7 Address Space of Control/Status Registers .
Page 8 9.2.1 Module Display Control Register ....9–5 9.2.2 Module Conﬁguration Register ....9–6 Interrupt and Interrupt Mask Registers 1, 2, 3, 4 .
Page 9 10.2.3 Interprocessor Communication ....10–14 10.2.3.1 Interprocessor Communication Registers ..10–14 Interprocessor Communication Global Switches . . . 10.2.3.2 10–14 Interprocessor Communication Module...
Page 10 11.2 Module Reset ........11–13 12 Console Primer 12.1 About the Console .
Page 11 echo ......... . 13–30 eval .
Page 12 sp ......... . . 13–100 start .
Page 13 2–15 Connecting the PMC I/O Companion Card ..2–26 Installing the PMC I/O Companion Card ... 2–16 2–27 3–1 Controls and Indicators ......3–2 Loopback Descriptions for Interval Timer Test 3 and 4–1...
Page 14 6–20 Refresh Timing Register: 0x180000220 ... . 6–29 Block Diagram of the DECchip 21071-BA ..6–21 6–30 7–1 PCI Host Bridge ......7–1 DECchip 21071-DA Block Diagram .
Page 15 9–14 82C54 Timer Data Access ..... . 9–28 Timer Clocking ....... 9–15 9–31 9–16...
Page 16 11–11 VIC Error Group ICR ......11–10 VMEbus Interrupter ICR ..... . . 11–12 11–10 11–13...
Page 17 3–1 Controls and Indicators ......3–2 Environment Variable Summary ....3–2 3–4 4–1...
Page 18 9–2 Module Conﬁguration Register ....9–7 DIMM Identiﬁcation ......9–3 9–9 9–4...
Page 19 11–1 Table of CPU Interrupt Assignments ....11–1 VIC64 Chip Interrupt Ranking ....11–2 11–6 11–3...
Page 21: Preface
Preface Purpose of this Manual This manual describes the Digital Alpha VME 4 module. It provides conﬁguration and installation procedures and describes the module’s built-in features, including the console code and diagnostics. Intended Audience This manual is for OEM system integrators who have extensive knowledge of single-board computers (SBCs).
Page 22 • Chapter 3, Operating the Digital Alpha VME 4 Computer, explains how to use the Digital Alpha VME 4 module’s controls and indicators, introduces console mode and environment variables, and provides pointers to information on booting operating systems and updating ﬁrmware. •...
Page 23 Conventions This section deﬁnes terminology, abbreviations, and other conventions used in this manual. Abbreviations • Register access The following list describes the register bit and ﬁeld abbreviations: Bit/Field Abbreviation Description MBZ (must be zero) Bits and ﬁelds speciﬁed as MBZ must be zero. RO (read only) Bits and ﬁelds speciﬁed as RO can be read but not written.
Page 24 Caution Cautions indicate potential damage to equipment or loss of data. Data Field Size The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data ﬁeld of nn contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a NATURALLY ALIGNED longword.
Page 25 Names and Symbols The following table lists typographical conventions used for names of various items throughout this manual. Items Example Bits sysBus<32:2> Commands boot command Command arguments address argument Command options -sb option Environment variables AUTO_ACTION Environment variable values HALT /usr/foo/bar Files and pathnames Pins...
Page 26 Syntax The following syntax elements are used throughout this manual. Do not type the syntax elements when entering information. Element Example Description [-ﬁle ﬁlename] The enclosed items are optional. - | + | = Choose one of two or more items. Select one of the items unless the items are optional.
Page 27 Operations that produce UNPREDICTABLE results might also produce exceptions. An occurrence specifed as UNPREDICTABLE might happen or not based on an arbitrary choice function. The choice function is subject to the same constraints as are UNPREDICTABLE results and, in particular, must not constitute a security hole.
Page 28 For More Information Document Order Number Company CY7C9640 Speciﬁcation Cypress Semiconductor Corp. DECchip 21040–AA Speciﬁcation EC–N0752–72 Digital Equipment Corp. DECchip 21064–AA Microprocessor Hardware EC–N0079–72 Digital Equipment Reference Manual Corp. DECchip 21072–AA Core Logic Chip Set EC–N0648–72 Digital Equipment Corp. Digital UNIX Installation Guide AA–PS2DD–TE Digital Equipment Corp.
Page 29: Product Overview
Product Overview 1.1 Product Description The Digital Alpha VME 4/224 and 4/288 MHz single-board computers are based on the 21064A Alpha processor chip. The Digital Alpha VME 4/224 comes preconﬁgured with 512 KB cache, and the Digital Alpha VME 4/288 comes preconﬁgured with 2 MB cache.
Page 30: Digital Alpha Vme 4 Functional Speciﬁcations
Table 1–1 Digital Alpha VME 4 Functional Speciﬁcations Item Description Alpha AXP processor 21064A Alpha processor with on-chip 16 KB instruction and 16 KB data caches IEEE and VAX ﬂoating point. Peformance At 288 MHz, 238.51 SPECfp92, 188.84 SPECint92, 5.44 SPECfp95, and 4.69 SPECint95.
Page 31: Digital Alpha Vme 4 Block Diagram
Figure 1–1 Digital Alpha VME 4 Block Diagram Cache and Memory Controller memdata Main Memory Data Path sysBus 128 Bits Bcache 4 chips PCI Host Bridge epiData (21071-DA) CPU Board (DS1386) I/O Board TOY Clock Interrupt Watchdog Timer Flash Controller NVRAM PCI to Nbus...
Page 32: Physical And Environmental Requirements
1.3 Physical and Environmental Requirements The Digital Alpha VME 4 module requires a VME chassis with sufﬁcient cooling. You must have at least 200 linear feet/minute (lfm) of airﬂow at an ambient temperature of not more than 40°C (104°F) across the processor heatsink. Table 1–2 shows the physical and environmental speciﬁcations for the Digital Alpha VME 4 module.
Page 33: Typical Peak Power Supply Current And Module Power Dissipation
Table 1–3 Typical Peak Power Supply Current and Module Power Dissipation CPU Modules Amps Amps @ 12 V Amps Module Heat w/128 MB Memory @ 5 V (note 1) @ 12 V Dissipation Alpha VME 4/224 12.0 A 0.2 A 0.01 A 62 W Alpha VME 4/288...
Page 35: Installation Procedures
Installation Procedures This chapter describes how to unpack, conﬁgure, install, and verify proper operation of the Digital Alpha VME 4 module. 2.1 Unpacking Your Digital Alpha VME 4 hardware kit contains the items listed in Table 2–1. Save the original packing material in case a factory return is necessary. Caution You must install the primary breakout module (54-24663-01) included in your hardware kit (see Figure 2–7).
Page 36: Digital Alpha Vme 4 Module Components
Figure 2–1 Digital Alpha VME 4 Module Components MLO-013240 Optional PMC I/O companion card I/O module Digital Alpha VME 4 module Memory modules Cache memory modules Secondary breakout module Primary breakout module Table 2–1 lists Digital Alpha VME 4 hardware kit items. The kits in Table 2–1 contain hardware only.
Page 37: Digital Alpha Vme 4 Hardware Kit Items
Table 2–1 Digital Alpha VME 4 Hardware Kit Items Item Part Number Digital Alpha VME 4/224 Kit Digital Alpha VME 4 module I/O assembly 70–32976–04 (includes 512 KB cache) (54–24325–04 + 54–24319–01) Digital Alpha VME 4 Primary breakout module 54–24663–01 Digital Alpha VME 4 Secondary breakout module 54–24729–01...
Page 38: Digital Alpha Vme 4 Memory Modules
Table 2–2 Digital Alpha VME 4 Memory Modules Memory Size (MB) Kit Number Part Number EBMXM-DB 54–24659–AB EBMXM-EB 54–24659–AA EBMXM-FB 54–24645–AA Table 2–3 Digital Alpha VME 4 Cache Memory Modules Memory Size Kit Number Part Number Quantity 512 KB EBMXC–BA 54–24685–AA 2 MB EBMXC–DB...
Page 39: Additional Hardware Installation Items
Table 2–4 Additional Hardware Installation Items Item Supplier Part Number Serial line cable for console and auxiliary Digital BC16E– nn terminals IEEE 802.3 Twisted-pair transceiver to ThinWire Digital DETTR–AA IEEE 802.3 Twisted-pair transceiver to twisted- Digital DETTR–BB pair 10BASET loopback connector Digital 12-35619-01 (H4082-AA)
Page 40: Installation
2.2 Installation To install the Digital Alpha VME 4 module, perform the following steps: 1. Select two adjacent slots in your VME backplane for the Digital Alpha VME 4 module. If you are installing a PMC I/O companion card, you will need to select three adjacent slots.
Page 41: Digital Alpha Vme 4 Module Layout
Figure 2–2 Digital Alpha VME 4 Module Layout 2 MB 512 KB 512 KB 2 MB MLO-013237 Cache memory connectors Memory connectors Cache conﬁguration select jumper (J9) Power and VME slave activity/watchdog timeout LEDs Status display Cache memory size and speed select jumper (J10) I/O module connector VME connectors SROM (8 pin)
Page 42: I/O Module Layout
Figure 2–3 I/O Module Layout OPEN MLO-013238 Console serial port Auxiliary serial port Reset/halt switch Twisted pair Ethernet connector Connector to CPU module (on back of I/O module) Debug jumper (not installed for normal operation) Conﬁguration switchpack PMC I/O companion card connector Ethernet Address ROM NVRAM/TOY clock 2–8 Installation Procedures...
Page 43: Digital Alpha Vme 4 Module Conﬁguration Switches
2. Set the conﬁguration switches on the I/O module as outlined in Table 2–5, Table 2–6, and Table 2–7. Also refer to Figure 2–3 for the conﬁguration switch location. Table 2–5 Digital Alpha VME 4 Module Conﬁguration Switches Switch Setting Function Closed Supplies +5 V from the VMEbus +5 V Standby signal to the time-...
Page 44: Supported Switch Settings For Digital Alpha Vme 4 Modules In Other Than Slot 1 (Nonsystem Controller)
Table 2–7 Supported Switch Settings for Digital Alpha VME 4 Modules in Other Than Slot 1 (Nonsystem Controller) Switch Setting Closed Open Closed Open These switches are required to be in the indicated positions (one opened, one closed) for reliable system operation during a VMEbus Reset.
Page 45: Installing The Main Memory Modules
Figure 2–4 Installing the Main Memory Modules MLO-013246 Memory bank 0 slots A and B Memory bank 1 slots A and B Orientation notches Memory connector Table 2–8 shows all possible valid memory conﬁgurations. Installation Procedures 2–11...
Page 46: Digital Alpha Vme 4 Memory Conﬁgurations
Table 2–8 Digital Alpha VME 4 Memory Conﬁgurations Memory Size Bank 0 Bank 0 Bank 1 Bank 1 (MB) Slot A Slot B Slot A Slot B 4. Cache memory DIMMs are installed on your Digital Alpha VME 4 module by Digital.
Page 47: Cache Memory Modules
Figure 2–5 Cache Memory Modules MLO-013245 Orientation notch Cache memory connector 5. The J9 and J10 jumpers are preconﬁgured for your Digital Alpha VME 4 module by Digital. Table 2–9, Table 2–10, and Figure 2–2 show jumper settings and locations for informational purposes only. Table 2–9 J9 Cache Jumper Settings Size 512 KB...
Page 48: J10 Cache Jumper Settings
Table 2–10 J10 Cache Jumper Settings Total Size Speed Disable cache Reserved 2 MB 12 ns Reserved 512 KB 15 ns Reserved Reserved Reserved Note If you are installing the PMC I/O companion card, proceed to Section 2.2.1 later in this chapter and complete the installation instructions before continuing on to step 6.
Page 49: Installing The Digital Alpha Vme 4 Module
Figure 2–6 Installing the Digital Alpha VME 4 Module MLO-013236 Caution You must install the primary breakout module (54-24663-01) included in your hardware kit (see Figure 2–7). Applying power to the Digital Alpha VME 4 module WITHOUT that primary breakout module in place, or WITH the breakout module included with the AXPvme 160, 166, or 230 (P/N 54–22605–01) in place may damage your backplane, the Digital Alpha VME 4 module, or both.
Page 50: Alpha Vme 4 Primary Breakout Module
Figure 2–7 Alpha VME 4 Primary Breakout Module Part Number: 54-24663-01 Part Number: 54-22605-01 MLO-013263 7. Set the SCSI termination jumper on the breakout module (refer to Figure 2–8). The SCSI bus must be terminated at each end. In most installations, the breakout module is one end of the SCSI bus and the far end of the SCSI ribbon cable is the other end of the SCSI bus.
Page 51: Primary Breakout Module Jumpers
component. The monitoring device must also be connected to the same ground reference as the Digital Alpha VME 4 module. The external watchdog reset signal is on pin C10 of the VMEbus J3 (P2) connector on the breakout module. This signal is low during normal operation and high during a watchdog timer reset (provided that pullup power is connected).
Page 52: Connecting The Scsi Cable To The Primary Breakout Module
Figure 2–9 Connecting the SCSI Cable to the Primary Breakout Module MLO-013241 10. Install the primary breakout module (refer to Figure 2–10). Ensure that the breakout module is installed behind the slots occupied by the Digital Alpha VME 4 module (as shown). Caution Running the Digital Alpha VME 4 module when it is not in the same slots as the correct breakout module (refer to Figure 2–10) may damage your...
Page 53: Installing The Primary Breakout Module
Figure 2–10 Installing the Primary Breakout Module MLO-013264 11. A secondary breakout module is included in the hardware kit, which you can connect to the primary breakout module. If you use the secondary breakout module, set the jumpers on that module as shown in Figure 2–11. Note An incremental clearance of at least 56.25 mm (2.25 inches) is required to install the secondary breakout module.
Page 54: Secondary Breakout Module Jumpers
Figure 2–11 Secondary Breakout Module Jumpers Keyboard / Mouse Keyboard / Mouse Disabled Enabled MLO-013353 Mouse and keyboard connector Mouse and keyboard Y cable (17-04230-01) Keyboard and mouse jumper conﬁgurations Parallel port (see Appendix A for pinouts) 12. Connect the secondary breakout module to the primary breakout module as shown in Figure 2–12.
Page 55: Connecting The Secondary Breakout Module To The Primary Breakout Module
Figure 2–12 Connecting the Secondary Breakout Module to the Primary Breakout Module MLO-013266 Primary breakout module (54-24663-01) Secondary breakout module (54-24729-01) 13. Connect the network cable (if any) to the twisted-pair Ethernet connector. See Figure 2–13. Associated with the Ethernet connector are devices to convert from twisted pair to ThinWire (P/N DETTR–AA).
Page 56: Connecting Network And Console Terminal Cables
Figure 2–13 Connecting Network and Console Terminal Cables MLO-013352 Network Console Auxiliary 16. Insert blank panels into the vacant slots of the VME chassis. This improves airﬂow and reduces electromagnetic interference (EMI) radiation. 17. Your installation is complete and power can be turned on. 18.
Page 57: Installing The Pmc I/O Companion Card
2.2.1 Installing the PMC I/O Companion Card Figure 2–14 shows the layout of the PMC I/O companion card. Note To install the PMC I/O companion card with the Digital Alpha VME 4, you must have three adjacent slots available. Figure 2–14 PMC I/O Companion Card Layout 3.3 V 5.0 V MLO-013366...
Page 58 Signaling level jumper (jumper MUST be set to 5.0 V) PMC option slots VME connectors I/O-to-P2 signal connector Caution Perform the following steps gently to avoid damage to the modules. 1. Make sure the signaling-level jumper on the PMC I/O companion card is set for 5.0 V, as show in Figure 2–14.
Page 59 seating the Alpha VME module in the VME chassis. If you do not retract the screws completely: • The Alpha VME module might not seat properly. • The press-ﬁt shoulder washer that holds the screw washer in place might become disengaged if you apply excessive pressure to the front panel.
Page 60: Connecting The Pmc I/O Companion Card
Figure 2–15 Connecting the PMC I/O Companion Card MLO-013265 2–26 Installation Procedures...
Page 61: Diagnostics
Figure 2–16 Installing the PMC I/O Companion Card MLO-013411 9. Return to step 6 in Section 2.2 for instructions on installing the Digital Alpha VME 4 module into the VME chassis and setting up and installing the breakout modules. 2.3 Diagnostics When you turn on the power or toggle the Reset switch, the Digital Alpha VME 4 module runs its POST.
Page 62: Srom Test Numbers And Descriptions
Table 2–11 SROM Test Numbers and Descriptions LED Display COM1 Meaning Nbus bus has been reset and SIO conﬁgured. COM1 port has been initialized (9600 baud). BIU_CTL register has been programmed according to the cache conﬁguration jumpers, but Bcache is not on line.
Page 63: Troubleshooting
Table 2–12 Console Code Test Letters and Names Test Letter Test Name SCSI control and status register (CSR) test Heartbeat timer test Interval timer test DS1386 nonvolatile RAM tests Auxiliary Universal Asynchronous Receiver/Transmitter (UART) test Ethernet address ROM test Ethernet internal and external loopback tests Watchdog timer test VME interface processor/VIC64 test After the POST completes and the system is idle, the console outputs a ‘‘rotating...
Page 64 If all SROM and ﬂash ROM-based diagnostics pass, and an auto_action boot command has been set, the >>> console prompt appears on the console terminal and the dot matrix display will display a ‘‘rotating bar.’’ Note that a problem in the PMC I/O companion card that hangs the PCI bus signal lines could cause diagnostics to report problems throughout the I/O subsystem and in the PCI controller of the processor chip.
Page 65: Troubleshooting
Table 2–13 Troubleshooting Symptom Corrective Action No LEDs lit, no console prompts. Check power. If 5 V power is out of speciﬁcation, the module will be held in reset. Green LED on, blank dot matrix display, Check the seating of SROM (8-pin socketed and no console prompts device near PCI port).
Page 66: Repair And Warranty Information
2.5 Repair and Warranty Information 2.5.1 Return to Digital Hardware Maintenance The following products come with a 1 year Return to Digital warranty as described in the following sections: Table 2–14 Products With a 1 Year Return to Digital Warranty Product Order Number Alpha VME 4/224, SBC...
Page 67: Return-To-Digital Process
2.5.2.2 Return-to-Digital Process To return products under warranty, contact the Digital Customer Support Center in your particular geography. The Customer Support Center provides you with a Return Material Authorization (RMA#) and an address to which to send the defective material. You are responsible for sending the product to the address provided and for prepaying transportation costs associated with returning the product to the nearest Digital return center.
Page 68: Pre-Call Checklist
• Assume all risk of loss or damage to ﬁeld replaceable units in transit to Digital. 2.5.2.6 Pre-Call Checklist To allow Digital to assist you quickly and efﬁciently, consult the following checklist before calling Digital or your authorized reseller: 1. Consult your product user documentation to assure that your system features are properly conﬁgured.
Page 69: Field Replaceable Units And Order Numbers
2.5.4 Field Replaceable Units and Order Numbers Table 2–15 lists the available ﬁeld replacable units and their associated order numbers. Table 2–15 Field Replaceable Units and Order Numbers Saleable Number Order Number Description EBV14-*A 70-32976-04 224 MHz Single Board Computer — 2 board set, 512 KB cache 54-24729-01 VME Secondary Breakout Module...
Page 71: Operating The Digital Alpha Vme 4 Computer
Operating the Digital Alpha VME 4 Computer 3.1 Controls and Indicators Figure 3–1 shows the front panel controls and indicators of the Digital Alpha VME 4 module and Table 3–1 describes their function. Operating the Digital Alpha VME 4 Computer 3–1...
Page 72: Controls And Indicators
Figure 3–1 Controls and Indicators MLO-013262 Table 3–1 Controls and Indicators Control or Indicator Description Reset/Halt switch A switch that resets the Digital Alpha VME 4 system when pressed in the Reset (up) direction. When pressed in the Halt (down) direction this switch halts the operating system and the module enters console mode.
Page 73: Console Mode
3.2 Console Mode Sections 3.2.1 and 3.2.2 explain how a Digital Alpha VME 4 system enters and exits console mode. 3.2.1 Entering Console Mode A Digital Alpha VME 4 module enters console mode automatically when the POST is ﬁnished. A Digital Alpha VME 4 module also enters console mode when: •...
Page 74: Environment Variable Summary
Note Do not change the settings of the environment variables without understanding the implications of the changes. Table 3–2 lists the environment variables with descriptions. Table 3–2 Environment Variable Summary Variable Description AUTO_ACTION Deﬁnes the action of the console following an error, halt, or power-up.
Page 75 Table 3–2 (Cont.) Environment Variable Summary Variable Description D_EOP Speciﬁes whether end-of-pass messages are to be displayed. D_GROUP Speciﬁes the diagnostic group to be executed. D_HARDERR Deﬁnes the action that is to be taken following a hard error detection. D_OPER Speciﬁes whether an operator is present.
Page 76 Table 3–2 (Cont.) Environment Variable Summary Variable Description EWA0_DEF_SINETADDR Speciﬁes the initial value for EWA0_SINETADDR when the interface’s internal Internet database is initialized from BOOTP (EWA0_INET_INIT is set to BOOTP). EWA0_INET_INIT Speciﬁes whether the interface’s internal Internet database is to be initialized from non-volatile RAM (NVRAM) or from a network server (by way of BOOTP).
Page 77: Booting An Operating System
Table 3–2 (Cont.) Environment Variable Summary Variable Description VME_A32_BASE Speciﬁes the base address of VMEbus A32 space. VME_A32_SIZE Speciﬁes the size of VMEbus A32 space. VME_A24_BASE Speciﬁes the base address of VMEbus A24 space. VME_A24_SIZE Speciﬁes the size of VMEbus A24 space. VME_A16_BASE Speciﬁes the base address of VMEbus A16 space.
Page 79: Diagnostics
Diagnostics 4.1 Overview This chapter describes the Digital Alpha VME 4 power-on self-test (POST) diagnostics and additional ROM-based diagnostics (RBDs). Diagnostics for the Digital Alpha VME 4 system provide a fast, high coverage suite of POSTs to be invoked automatically at power-on and system reset. In addition to the POSTs, there are RBDs that provide additional testing and fault isolation.
Page 80: Console Prompt Diagnostics
Failures detected by the SROM-based tests are indicated by the test sequence halting and the LED display permanently showing the failing test number. A detailed dump of internal registers, program counter, expected and actual data is performed either through the serial port of the 21064 or through the console Universal Asynchronous Receiver/Transmitter (UART).
Page 81: Console Diagnostic Tests
Table 4–1 Console Diagnostic Tests HW Under Test Command Memory and Cache - Memory exerciser test memtest or mem_ex Network Interface - DECchip 21040 network interface niil_diag -t 1 internal loopback test - DECchip 21040 network interface niil_diag -t 2 external loopback test - DECchip 21040 network interface control nicsr_diag -t 1...
Page 82: Srom Initialization Countdown
Table 4–1 (Cont.) Console Diagnostic Tests HW Under Test Command - SCSI device exer exer dk Timers - Heartbeat timer test hbeat_diag -t 1 - Interval timer test i8254 -t 1 - Interval timer test i8254 -t 2 - Interval timer test i8254 -t 3* - Interval timer test i8254 -t 4*...
Page 83: Console Post Descriptions
Output on LED Display Console Meaning – Nbus bus has been reset and system I/O (SIO) conﬁgured. COM1 port has been initialized (9600 baud). BIU_CTL register has been programmed according to the cache conﬁguration jumpers, but Bcache was not enabled. Main memory controller has been conﬁgured according to the DIMM PD/ID bits.
Page 84: Post Non-Volatile Ram Diagnostic
POST Non-Volatile RAM Diagnostic POST Non-Volatile RAM Diagnostic The POST Non-Volatile RAM (NVRAM) diagnostic test veriﬁes the module’s NVRAM. It performs a data integrity test, through power cycles, and a write /read/compare of speciﬁc NVRAM locations used for diagnostics. It also checks for uninitialized NVRAM by comparing the stored checksum with the calculated checksum.
Page 85: Post Memory Diagnostic
POST Memory Diagnostic POST Memory Diagnostic The POST memory diagnostic test veriﬁes system memory. It runs with ECC enabled. If the test detects a memory error that cannot be corrected with ECC, it logs the error in the error logging area of NVRAM. Description See also memtest in Chapter 13.
Page 86: Console Diagnostic Test Descriptions
4.3.4 Console Diagnostic Test Descriptions This section provides details on the tests, which are available to the console, that you might run during system initialization testing or run from the console. 4–8 Diagnostics...
Page 87: Heartbeat Timer Test
Heartbeat Timer Test Heartbeat Timer Test The heartbeat timer diagnostic test veriﬁes that a heartbeat interrupt is generated at the correct interval (1024 Hz) and is properly dismissed by way of the module clear heartbeat register. This test checks the following logic: •...
Page 88: Interval Timer Tests
Interval Timer Tests Interval Timer Tests The interval timer tests test the functionality of the 8254 interval timer chip and surrounding external circuitry, including latches, programmable-array logic (PAL) devices and printed circuit board module etch. Since all three interval timers of the 8254 chip have different external conﬁgurations, several tests are required for complete test coverage.
Page 89 Interval Timer Tests • See the Intel 8254 interval timer sheet for more details. Timer 2 Square Wave Test This test exercises timer 2. In the Digital Alpha VME 4 design, the gate input for timer 2 is always enabled and the clock input is connected to a 10 MHz (100 ns period) clock source.
Page 90 Interval Timer Tests This test essentially emulates the realtime time provider and slave scheme found in the Realtime Clock and Interval Device Driver functional speciﬁcation. Note A VMEbus P2 loopback connector is required. See Figure 4–1 for a description of the loopback connections. Using the -lp option enables the timers indeﬁnitely, making the module the master time provider for test #4.
Page 91 Interval Timer Tests This test enables only timer 0 as done in test 3 but does not use timer 1 or timer 2. The clock and gate come from the timers on the master Digital Alpha VME 4 module. Timer 0 interrupts when the gate is received and its count is decremented to 0.
Page 92 Interval Timer Tests • Due to hardware limitations on interrupt detection, the value programmed into timer 2 must be greater than 2. • See the Intel 8254 interval timer sheet for more details. Timer 1 Interrupt Test This test veriﬁes the interrupt path of timer 1 (periodic RT timer). Timer 1 is programmed to mode 3, square wave mode.
Page 93: Loopback Descriptions For Interval Timer Test 3 And
Interval Timer Tests Figure 4–1 Loopback Descriptions for Interval Timer Test 3 and 4 Configuration for Interval Timer test 3 To make a loopback for test 3 connect pin C11 to C14. With a second jumper, connect C12 to C13. (VMEbus P2 Connector) row C 14 13...
Page 94: Decchip 21040 Ethernet Controller Tests
DECchip 21040 Ethernet Controller Tests DECchip 21040 Ethernet Controller Tests These diagnostics verify that the internal and external loopback mechanisms are properly operating in the DECchip 21040 Ethernet controller chip as well as performing writes and reads to all conﬁguration registers. Ethernet Internal Loopback Test The NI internal loopback test transmits Ethernet packets from the transmit ring in main memory, loops them back at the MAC layer and returns them to the...
Page 95 DECchip 21040 Ethernet Controller Tests DECchip 21040 PCI Conﬁguration Register Dump This test reads the PCI conﬁguration registers of the DECchip 21040 and prints them to the standard output. Console Command: nicsr_diag -t 1 DECchip 21040 Control/Status Register Dump This test reads the CSRs of the DECchip 21040 and prints them to the standard output.
Page 96: Dallas Ds1386 Ramiﬁed Watchdog Timekeeper Tests
DALLAS DS1386 RAMiﬁed Watchdog Timekeeper Tests DALLAS DS1386 RAMiﬁed Watchdog Timekeeper Tests The DS1386 consists of 32 KB of NVRAM and a realtime clock. This diagnostic tests each of these features on an individual basis. The diagnostic tests the DS1386, decoders, and printed circuit board module etch. The functionality of the watchdog feature is to be tested in a separate diagnostic.
Page 97 DALLAS DS1386 RAMiﬁed Watchdog Timekeeper Tests NVRAM Address-On-Address Test The NVRAM locations in the DS1386 are byte wide. Therefore, you do not have enough room to write the unique address into each corresponding location. However, this test writes the unique page offset to its corresponding location in NVRAM.
Page 98 DALLAS DS1386 RAMiﬁed Watchdog Timekeeper Tests Console Command: ds1386_diag -t 3 Command Options: • -dd: print detailed test information on each pass. • -nqv: test every location in NVRAM, default is to test 1 location per 256 byte page. Miscellaneous Note This diagnostic is an extended test.
Page 99 DALLAS DS1386 RAMiﬁed Watchdog Timekeeper Tests Console Command: ds1386_diag -t 4 Command Option: -dd: print detailed test information on each pass. Miscellaneous Note This diagnostic is an extended test. TOY Clock Time Advancement Test This diagnostic is a power-on diagnostic. It veriﬁes that the TOY clock registers are advancing with clock ticks.
Page 100: Local Area Network Address Rom Test
Local Area Network Address ROM Test Local Area Network Address ROM Test This diagnostic tests the integrity of the Local Area Network (LAN) address ROM, decoders, and printed circuit board module etch. The LAN address ROM contains the Ethernet station address of the module. LAN Address ROM Dump This diagnostic dumps the contents of the 32 octets within the LAN address ROM to the screen.
Page 101: Lan Address Rom Format
Local Area Network Address ROM Test Figure 4–2 LAN Address ROM Format Address Octet 0 Address Octet 1 Address Octet 2 Address Octet 3 Address Octet 4 Address Octet 5 Checksum Octet 1 Checksum Octet 2 Checksum Octet 2 Checksum Octet 1 Address Octet 5 Address Octet 4 Address Octet 3...
Page 102: Ncr 53C810 Pci-Scsi I/O Processor Tests
NCR 53C810 PCI-SCSI I/O Processor Tests NCR 53C810 PCI-SCSI I/O Processor Tests These tests check the NCR810 SCSI controller chip. The tests do not require a drive to be attached to the SCSI port and are meant to be a power-on check of the NCR810 chip’s low-level modes through programmed I/O issued from the CPU.
Page 103 NCR 53C810 PCI-SCSI I/O Processor Tests NCR810 Command/Status Register Test This test writes, reads, and compares all of the NCR810 command/status registers that are feasible to test. When the test ﬁnishes, it returns the registers to their initialized values. Console Command: ncr810_diag -t 3 Command Option: -lp: loop on write/read if the -lp option is speciﬁed.
Page 104 NCR 53C810 PCI-SCSI I/O Processor Tests NCR810 Interrupt Test This test veriﬁes the interrupt connection between the NCR810 and the SIO controller to the CPU. A general purpose timer is enabled which generates an interrupt that is dispatched to the CPU through the SIO controller. The console PALcode dispatches to the NCR810_diag ISR, which clears the interrupt.
Page 105: Watchdog Timer Interrupt Test
Watchdog Timer Interrupt Test Watchdog Timer Interrupt Test This test veriﬁes the functionality of the watchdog timeout by its ability to handle a user programmed watchdog reset. This test checks the following logic: • Watchdog timer • Some reset logic •...
Page 106: Vme Interface Tests
VME Interface Tests VME Interface Tests These tests verify the VME interface logic on the Digital Alpha VME 4 module, including the VME interface processor (VIP), the Cypress VIC064, the scatter/gather RAMs, and some of the interrupt paths from the VME corner to the Alpha processor.
Page 107 VME Interface Tests VME Scatter-Gather RAM Test This test veriﬁes the integrity of the scatter/gather RAM by performing write, read, and verify of various patterns to the entire scatter/gather RAM. Console Command: vip_diag -t 4 Command Option: -dd: print detailed test information on each pass. Diagnostics 4–29...
Page 108: Initialization Sequence
4.4 Initialization Sequence The diagnostic test sequence for a full power-on reset and initialization is shown in Figures 4–3, 4–4, and 4–5. Figure 4–3 SROM Test Flows Power-on/Reset Notes Display Serial ROM Initialize 21064 and 21072 chipset Initialize SIO chip Serial ROM Serial ROM Console serial port initialization...
Page 109: Console Post Flows
Figure 4–4 Console POST Flows Notes Display Console test SCSI Test Console test Heartbeat Test Console test Interval Timer Tests Time-of-Year Tests Console test Console test Serial Com Port Tests Ethernet ROM Tests Console test Ethernet Internal Loopback Console test Tests ML013409 Diagnostics 4–31...
Page 110: Console Post Flows
Figure 4–5 Console POST Flows Notes Display Console test Watchdog Test Console test VIP-VIC Tests Console Prompt Console test ML013410 4–32 Diagnostics...
Page 111: System Address Mapping
System Address Mapping This chapter describes the mapping of the 34-bit processor physical address space into memory and I/O space addresses. It also includes the translations of the processor-initiated address into a PCI address, and PCI-initiated addresses into physical memory addresses. 5.1 CPU Address Mapping to PCI Space The 34-bit physical system bus (sysBus) address space is composed of the following:...
Page 112: System Bus Address Map
Figure 5–1 System Bus Address Map 2 0000 0000 1 C000 0000 Flash ROM 0 0000 0000 Cacheable 2 000F FFFF 1 C001 FFFF Memory Space 0 FFFF FFFF 1 C008 0000 Programmed Ethernet Timers 1 0000 0000 by Firmware Noncacheable 1 C00B FFE0 Memory...
Page 113: System Bus Address Space Description
Table 5–1 System Bus Address Space Description sysAdr sysAdr <33:32> <31:28> Address Space Description xxxx Cacheable memory Accessed by the CPU instruction stream space (Istream) or data stream (Dstream). Accessed by direct memory access (DMA). 0xxx Noncacheable Accessed by the CPU (Istream or memory space Dstream).
Page 114: Cacheable Memory Space (0X000000000 To 0X0Ffffffff)
Table 5–1 (Cont.) System Bus Address Space Description sysAdr sysAdr <33:32> <31:28> Address Space Description xxxx PCI sparse memory 128 MB addressable PCI space. The space lower address bits are used to determine byte masks and transaction length information. The 4 GB space is reduced to a 128 MB sparse space.
Page 115: Decchip 21071-Da Csr Space (0X1A0000000 To 0X1Afffffff)
5.1.4 DECchip 21071-DA CSR Space (0x1A0000000 to 0x1AFFFFFFF) The DECchip 21071-DA responds to all accesses in this space. Section 7.4 speciﬁes the registers and associated register addresses. Section 7.5 contains the register descriptions. 5.1.5 PCI Interrupt Acknowledge/Special Cycle Space (0x1B0000000 to 0x1BFFFFFFF) A read access to this space causes an interrupt acknowledge cycle on the PCI.
Page 116: Pci Sparse I/O Space Address Translation
Figure 5–2 shows the translation of system bus addresses to PCI bus I/O addresses. Table 5–2 shows how the byte enable bits and PCI ad<2:0> are generated from bits sysBus<6:3>. Figure 5–2 PCI Sparse I/O Space Address Translation 29 28 23 22 08 07 05 04 03 02...
Page 117: Pci Sparse I/O Space Byte Enable Generation
Table 5–2 PCI Sparse I/O Space Byte Enable Generation PCI Byte Address Address Length <6:5> <4:3> Enable PCI ad<2:0> Byte 1110 CPU address<7>, 00 1101 CPU address<7>, 01 1011 CPU address<7>, 10 0111 CPU address<7>, 11 Word 1100 CPU address<7>, 00 1001 CPU address<7>, 01 0011...
Page 118: Pci Conﬁguration Space (0X1E0000000 To 0X1Ffffffff)
5.1.7 PCI Conﬁguration Space (0x1E0000000 to 0x1FFFFFFFF) A read or write access to this space causes a conﬁguration read or write cycle on the PCI. There are two classes of targets: devices on the primary PCI bus and devices on the secondary PCI buses that are accessed through PCI-to-PCI bridge chips.
Page 119: Pci Conﬁguration Cycles To Primary Bus Targets
Table 5–4 PCI Address Decoding for Primary Bus Conﬁguration Accesses Device Number (sysAdr<20:16>) PCI ad<31:11> 00000 0000 0000 0000 0000 0000 1 00001 0000 0000 0000 0000 0001 0 00010 0000 0000 0000 0000 0010 0 00011 0000 0000 0000 0000 0100 0 00100 0000 0000 0000 0000 1000 0 00101...
Page 120: Pci Conﬁguration Cycles To Secondary Bus Targets
Peripherals that integrate multiple functional units (for example, SCSI, Ethernet, and so on) can provide conﬁguration spaces for each function. Bits ad<10:8>, which are taken from bits sysAdr<15:13>, can be decoded by the peripheral to select one of eight functional units. Bits <31:11>...
Page 121: Pci Sparse Memory Space (0X200000000 To 0X2Ffffffff)
5.1.8 PCI Sparse Memory Space (0x200000000 to 0x2FFFFFFFF) Access to PCI sparse memory space can have byte, word, tribyte, longword, or quadword granularity. The Alpha architecture does not provide byte, word, or tribyte granularity, which the PCI requires. To provide this granularity, the byte enable and byte length information is encoded in the lower address bits of this space (ad<7:3>).
Page 122: Pci Memory Space Address Translation
Figure 5–3 PCI Memory Space Address Translation 32 31 29 28 08 07 04 03 02 0 0 0 Length in Bytes HAXR0 Longword Address Byte Offset 27 26 03 02 Address Translation for Lower 16M Bytes of PCI Memory Space 33 32 31 29 28 08 07...
Page 123: Pci Sparse Memory Space Byte Enable Generation
Table 5–5 PCI Sparse Memory Space Byte Enable Generation PCI Byte Length Address<6:5> Address<4:3> Enable PCI ad<2:0> Byte 1110 CPU address<7>, 00 1101 CPU address<7>, 00 1011 CPU address<7>, 00 0111 CPU address<7>, 00 Word 1100 CPU address<7>, 00 1001 CPU address<7>, 00 0011 CPU address<7>, 00...
Page 124: Pci Dense Memory Space (0X300000000 To 0X3Ffffffff)
One bit pair of cpucwmask<1:0>, <3:2>, <5:4>, and <7:6> must have a value of 01 (binary). The other ﬁelds must be 00. The location of the 01 ﬁeld indicates whether the data reference is byte, word, tribyte, or longword (respectively). Similarly, if a quadword is written to the PCI, software must execute an STQ instruction to the corresponding address.
Page 125: Pci-To-Physical Memory Addressing
• On write transactions, ad<4:2> is generated from cpucwmask<7:0>. If the lower longword is to be written, ad<2> is 0; if the lower longword is masked out and the upper longword is to be written, ad<2> is 1. The number of longwords written on the PCI is directly obtained from cpucwmask<7:0>.
Page 126: Pci Target Window Enables
Table 5–6 PCI Target Window Enables PCI_MASK<31:20> Window Size Value of n 0000 0000 0000 1 MB 0000 0000 0001 2 MB 0000 0000 0011 4 MB 0000 0000 0111 8 MB 0000 0000 1111 16 MB 0000 0001 1111 32 MB 0000 0011 1111 64 MB...
Page 127: Pci Target Window Compare Scheme
Figure 5–4 PCI Target Window Compare Scheme 20 19 13 12 PCI Address Peripheral Page Number Offset Compare PCI Base Register PCI Mask (Determines ) n 0000000 Register LJ-03955.AI When an address match occurs with a PCI target window, the 21071-DA translates the 32-bit PCI address ad<31:0>...
Page 128: Pci Target Address Translation-Direct Mapped
Table 5–7 PCI Target Address Translation—Direct Mapped PCI_MASK<31:20> Translated Base <32:5> 0000 0000 0000 T_BASE<32:20>:PCI ad<19:5> 0000 0000 0001 T_BASE<32:21>:PCI ad<20:5> 0000 0000 0011 T_BASE<32:22>:PCI ad<21:5> 0000 0000 0111 T_BASE<32:23>:PCI ad<22:5> 0000 0000 1111 T_BASE<32:24>:PCI ad<23:5> 0000 0001 1111 T_BASE<32:25>:PCI ad<24:5> 0000 0011 1111 T_BASE<32:26>:PCI ad<25:5>...
Page 129: Scatter-Gather Map Page Table Entry In Memory
Figure 5–5 Scatter-Gather Map Page Table Entry in Memory Page Address <32:13> Valid LJ03956A.AI The size of the scatter-gather map table is determined by the size of the PCI target window as deﬁned by the PCI mask register (see Table 5–8). Because the scatter-gather map is located in system memory, bit sysBus<33>...
Page 130: Scatter-Gather Map Address
Table 5–8 Scatter-Gather Map Address Scatter-Gather Scatter-Gather PCI_MASK<31:20> Table Size Map Address<32:3> 0000 0000 0000 1 KB T_BASE<32:10>:PCI ad<19:13> 0000 0000 0001 2 KB T_BASE<32:11>:PCI ad<20:13> 0000 0000 0011 4 KB T_BASE<32:12>:PCI ad<21:13> 0000 0000 0111 8 KB T_BASE<32:13>:PCI ad<22:13> 0000 0000 1111 16 KB T_BASE<32:14>:PCI ad<23:13>...
Page 131: Scatter-Gather Map Translation Of Pci Bus Address To System Bus Address
Figure 5–6 Scatter-Gather Map Translation of PCI Bus Address to System Bus Address 13 12 05 04 PCI Address Peripheral Page Number Offset Compare sysBus Base Address T_Base 0000 (Translated Base Register) Scatter-Gather Map Address Driven on sysBus Scatter-Gather Entry Scatter-Gather Map in Main Memory...
Page 133: Cache And Memory Subsystem
Cache and Memory Subsystem The cache and memory subsystem serves as the memory controller and the system bus (sysBus) controller. Figure 6–1 Cache and Memory Subsystem Cache and Memory Controller Main Memory Data Path System Bus (sysBus) Bcache 4 chips ML013274 The components of the cache and memory subsystem are distributed between the DECchip 21071-CA and the DECchip 21071-BA.
Page 134: Address And Data Paths Of Cache And Memory
Figure 6–2 Address and Data Paths of Cache and Memory Tag Adr Ctrl L2 Cache Ctrl 21071-CA Memory Address and Control SysAdr sysData <15:0> Cache Memory DRAMs sysData <127:0> Check <21:0> 32 Bits 32 Bits 32 Bits 32 Bits 21071-BA0 21071-BA1 21071-BA2 21071-BA3...
Page 135: Ca Block Diagram
Figure 6–3 21071-CA Block Diagram Write tagadr<31:17> Write Address Buffer Address Compare Address Read Address adr<33:5> Generation Row and b0<3:0>_adr<11:0> Column Generation b<3:0>_ras<1:0>_l Write Bank b<3:0>_ras<1:0>b_l Memory SysBus Control Bank SysBus b<1:0>_cas<3:0>b_l Read Bank Memory Generation L2 Cache Control Control L2 Cache Dath Path Control b0<3:0>_we_l...
Page 136: System Bus Interface
6.1 System Bus Interface The CPU, DECchip 21071-CA, PCI host bridge, cache, and memory communicate with each other through the system bus. The system bus is the processor pin bus with additional signals for DMA transaction control, arbitration, and cache control.
Page 137: Bcache Control
6.2 Bcache Control Figure 6–4 shows the implementation of a cache subsystem with a 2 MB cache. Figure 6–4 Cache Subsystem for a 2 MB Cache Bcache SIMMs (2 MB) AlphaPC64.10 FCT162244ET 21071-DA System Address Cache Cache/Memory Control Control Tag, Tag V, D, P 21071-CA Arrays CPU Cache Control...
Page 138: Memory Organization
6.3.1 Memory Organization A bank of memory is one width of DRAMs, 128 bits, implemented with DIMMs. The DECchip 21071-CA supports one or two banks of DRAM where each bank consists of two DIMMs of the same size and speed. The 21071-CA supports 16 MB to 128 MB of main memory.
Page 139: Memory Address Generation
6.3.2 Memory Address Generation Each bank has a programmable base address and size. The incoming physical address is compared with the memory ranges of all banks. The number of bits that are compared depends on the size of the bank. The programmable base address of a bank set must be aligned to the natural size boundary.
Page 140: Presence Detect Logic
6.3.7 Presence Detect Logic The DECchip 21071-CA supports loading the status of 32 presence detect bits from the memory conﬁguration registers 0 to 3 and the memory identiﬁcation register after reset. 6.4 Error Handling During CPU and DMA transactions, the DECchip 21071-CA detects the following errors: •...
Page 141: Csr Register Addresses For Decchip 21071-Ca
Table 6–1 identiﬁes all banks; only Bank 0 and 1 are used. Table 6–1 CSR Register Addresses for DECchip 21071-CA Address Register Name 1 8000 0000 General control register 1 8000 0020 Reserved 1 8000 0040 Error and diagnostic status register 1 8000 0060 Tag enable register 1 8000 0080...
Page 142 Table 6–1 (Cont.) CSR Register Addresses for DECchip 21071-CA Address Register Name 1 8000 0A40 Bank 2 conﬁguration register 1 8000 0A60 Bank 3 conﬁguration register 1 8000 0A80 Bank 4 conﬁguration register 1 8000 0AA0 Bank 5 conﬁguration register 1 8000 0AC0 Bank 6 conﬁguration register 1 8000 0AE0...
Page 143: Description Of Csrs
6.6 Description of CSRs 6.6.1 General Control Register The general control register contains status information that affects the memory, cache, and system bus controllers. The register is shown in Figure 6–6 and is deﬁned in Table 6–2. Figure 6–6 General Control Register: 0x180000000 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BC_BADAP BC_FRCP...
Page 144 Table 6–2 General Control Register Field Name Type Description <15:14> Reserved — <13> BC_BADAP RW, 0 Bcache force bad address parity. When set, the tag address parity is loaded as an invalid address, independent of the value of the BC_ FRCTAG bit.
Page 145: Error And Diagnostic Status Register
Table 6–2 (Cont.) General Control Register Field Name Type Description <5> BC_EN RW, 0 Bcache enable. When clear, the L2 cache is disabled and the cache state machine does not probe the cache. <4> WIDEMEM Wide memory size. Reads the status of the widemem input pin.
Page 146: Error And Diagnostic Status Register: 0X180000020
Figure 6–7 Error and Diagnostic Status Register: 0x180000020 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WRPEND LDXLLOCK PASS 2 CREQCAUSE VICCAUSE DMACAUSE NXMERR BC_TCPERR BC_TAPERR LOSTERR LJ-04179.AI Table 6–3 Error and Diagnostic Status Register Field Name Type...
Page 147 Table 6–3 (Cont.) Error and Diagnostic Status Register Field Name Type Description <8:6> CREQCAUSE Cycle request caused error. Indicates the DMA or CPU cycle request type that caused the error. Contains a copy of either the cpucreq or iocmd signal lines, depending on DMACAUSE<4>.
Page 148: Tag Enable Register
6.6.3 Tag Enable Register The tag enable register (TAGEN), shown in Figure 6–8, indicates which bits of the cache tag are compared to sysadr<33:5>: • If a bit is 1, the bits in sysadr<33:5> and systag<31:17> are compared. Bits <15:1> in the register represent systag<31:17>. •...
Page 149: Cache Size Tag Enable Values
Table 6–4 Cache Size Tag Enable Values Compared TAGEN<15:0> Bits Cache Size 0000 0000 0000 0000 None 4 GB 1000 0000 0000 0000 <31> 2 GB 1100 0000 0000 0000 <31:30> 1 GB 1110 0000 0000 0000 <31:29> 512 MB 1111 0000 0000 0000 <31:28>...
Page 150: Error Low Address Register
Table 6–5 Maximum Memory Tag Enable Values Compared TAGEN<15:0> Bits Memory Size 1111 1111 1111 1110 <31:17> 4 GB 0111 1111 1111 1110 <30:17> 2 GB 0011 1111 1111 1110 <29:17> 1 GB 0001 1111 1111 1110 <28:17> 512 MB 0000 1111 1111 1110 <27:17>...
Page 151: Error High Address Register
Figure 6–9 Error Low Address Register: 0x180000080 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ERR_LADR<20:5> LJ-04181.AI 6.6.5 Error High Address Register When an error sets the BC_TAPERR, BC_TCPERR, or NXMERR bit in the error and diagnostic status register, the error high address register latches the high- order bits of the sysadr<33:21>...
Page 152: Ldx_L High Address Register
Figure 6–11 LD x _L Low Address Register: 0x1800000C0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 LDXL_LARD<20:5> LJ-04183.AI 6.6.7 LD x _L High Address Register The LDx_L high address register stores the high-order bits of the latched address. The register is shown in Figure 6–12.
Page 153: Presence Detect High-Data Register
Figure 6–13 Presence Detect Low-Data Register: 0x180000280 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRES_DET<15:0> LJ-04186.AI 6.6.8.2 Presence Detect High-Data Register After a reset operation, presence detect data are shifted from the memory conﬁguration and memory ID.
Page 154: Conﬁguration Registers
Figure 6–15 Bank 0 Base Address Register: 0x180000800 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 S0_BASEADR<33:23> LJ-04188.AI The base address of each bank must begin on a naturally aligned boundary. For example, for a bank with 2 addresses, the n least signiﬁcant bits must be zero.
Page 155: Conﬁguration Register For Banks 0 And 1 . . . . . . . . . . 6-7 Timing Register A
Table 6–6 Conﬁguration Register for Banks 0 and 1 Field Name Type Description <15:9> Reserved — <8:6> S0_COLSEL Column address selection. Indicates the number of valid column bits expected at the DRAMs. Used with memory width information to generate row or column addresses.
Page 156: Bank Set Timing Registers
Table 6–6 (Cont.) Conﬁguration Register for Banks 0 and 1 Field Name Type Description <4:1> S0_SIZE Bank size in Mbytes. Indicates the size of the bank and any subbanks. The size deﬁnes which bits are used in comparing the base address with the physical address (PA) and for generating the subset.
Page 157: Bank Set 0 Timing Register A: 0X180000C00
The description of the parameters also indicates the corresponding DRAM parameter. Bank 0’s timing register A is shown in Figure 6–17 and is deﬁned in Table 6–7. Figure 6–17 Bank Set 0 Timing Register A: 0x180000C00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 S0_RDLYCOL S0_RDLYROW S0_COLHOLD...
Page 158: Bank Set 0 Timing Register B: 0X180000E00
Table 6–7 (Cont.) Timing Register A Field Name Type Description <6:4> S0_COLSETUP RW, 0 Column address setup (t ) to ﬁrst CAS assertion and write enable setup (t ) to CAS assertion. Used to determine ﬁrst b0_cas<1:0>_l assertion after column address and b<1:0>_cas<1:0>_l assertion after b0_l<3:0>_we_l.
Page 159: Global Timing Register
Table 6–8 Timing Register B Field Name Type Description <15:14> Reserved — <13:11> S0_WHOLD0COL RW, 1 Write hold time from column address. Used only for the ﬁrst data when starting in page mode. Write data is valid with the column address and is held valid for S8_WHOLD0COL + 2 cycles after the column address.
Page 160: Refresh Timing Register
Figure 6–19 Global Timing Register: 0x180000200 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 GTR_MAX_RAS_WIDTH GTR_RP LJ-04193.AI Table 6–9 Global Timing Register Field Name Type Description <15:6> Reserved — <5:3> GTR_MAX_RAS_WIDTH — Maximum RAS assertion width as a multiple of 128 memory clock cycles.
Page 161: Refresh Timing Register: 0X180000220
The refresh timing register is shown in Figure 6–20 and is deﬁned in Table 6–10. Figure 6–20 Refresh Timing Register: 0x180000220 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FORCE_REF REF_INTERVAL REF_RASWIDTH REF_CAS2RAS DISREF LJ-04194.AI...
Page 162: Data Path
Table 6–10 (Cont.) Refresh Timing Register Field Name Type Description <0> DISREF RW, 0 Disable refresh. Refresh operations are not performed when DISREF is set. The other timings in this register must not change while this bit is set. FORCE_REF overrides DISREF.
Page 163: Memory Read Buffer
6.7.1 Memory Read Buffer The memory read buffer stores data from memory before the data is sent to the CPU or returned to DMA in the DMA read buffer. Each chip stores 4 longwords of data and the corresponding ECC bits in the memory read buffer. 6.7.2 I/O Read Buffer and Merge Buffer On CPU-initiated memory transactions, the buffer acts as the merge buffer.
Page 164: Memory Write Buffer
6.7.5 Memory Write Buffer The memory write buffer has four entries for each chip. Each entry has four longwords and corresponding ECC bits. The system bus interface loads the buffer and the memory controller unloads it (both are 21071-CA functions). 6.7.6 Error Handling The data path chips perform ECC on DMA transactions.
Page 165: Pci Host Bridge
PCI Host Bridge The 21071-DA chip is the bridge between the PCI local bus and the system bus, as shown in Figure 7–1. Figure 7–1 PCI Host Bridge EpiData bus 32 Bits PCI Host Bridge (21071-DA) PCI BUS 32 Bits ML013280 As a PCI host bridge, the 21071-DA chip contains all control functions of the bridge and some data path functions.
Page 166: Interface To The System Bus
Figure 7–2 DECchip 21071-DA Block Diagram adr<33:5> Address DMA Write DMA Read MUX and I/O Read Data I/O Write Data Merge Logic Address 8-Entry PCI cbe<3:0> PCI Window Hit Detection Parity Check Generation PCI par epiErr<31:0> CSRs and Error Logging DMA Read Address 3 LW DMA Read...
Page 167: Buffering System Bus Transactions
7.1.2 Buffering System Bus Transactions Write-and-run I/O write transactions use a 1-entry write buffer. One I/O read transaction is initiated by the CPU. The I/O read buffer is a temporary buffer and is invalidated at the end of each I/O read transaction. To function correctly, the CPU must be conﬁgured in wrap mode.
Page 168: Burst Length And Prefetching For Pci Bus
7.2.3 Burst Length and Prefetching for PCI bus On write transactions directed toward main memory, the PCI host bridge supports a maximum burst length of 16 longwords. For the maximum burst, the write transaction must start on an even cache-line boundary with PCI ad<5> = 0 and PCI ad<4:2>...
Page 169: Data Coherency
7.3.3 Data Coherency The two agents that must synchronize their data transfers are the CPU and any PCI device. The PCI host bridge maintains data coherency and synchronization between the agents using the following mechanisms: • Maintains strict ordering of DMA write transactions initiated on the PCI bus. •...
Page 170: Interrupts
7.3.4 Interrupts When the PCI host bridge has errors to report, it uses the int_hw0 signal to interrupt the CPU. It does not distinguish between hard and soft errors when asserting the interrupt signal. The PCI host bridge does not provide an interval timer interrupt so this functionality must be provided to the CPU by some other device in the system.
Page 171: Retry Timeout
7.3.7 Retry Timeout The PCI host bridge implements a timeout mechanism to terminate CPU-initiated transactions that do not complete on the PCI bus because of too many disconnects or retries. When it initiates a CPU transaction on the PCI bus, the PCI host bridge counts the number of times it is retried or disconnected.
Page 172: Host Address Extension Register 1
Table 7–1 (Cont.) DECchip 21071-DA CSR Addresses Address Register Name 1 A000 0040 System bus error address register (SEAR) 1 A000 0060 Dummy register 1 1 A000 0080 Dummy register 2 1 A000 00A0 Dummy register 3 1 A000 00C0 Translated base 1 register 1 A000 00E0 Translated base 2 register...
Page 173: Description Of Csrs
Table 7–1 (Cont.) DECchip 21071-DA CSR Addresses Address Register Name 1 A000 03E0 TLB 7 data register 1 A000 0400 Translation buffer invalidate all register (TBIA) 7.5 Description of CSRs The CSRs are 16 bits wide and are addressed on cache-line boundaries. Write transactions to read-only registers could result in UNPREDICTABLE behavior;...
Page 174: Diagnostic Control/Status Register: 0X1A0000000
Figure 7–3 Diagnostic Control/Status Register: 0x1A0000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PASS2 PCMD D_BYP<1:0>...
Page 175 Table 7–2 (Cont.) Diagnostic Control/Status Register Field Name Type Description <17:16> RW, 0 Disable read bypass. Controls the order of PCI- BYP<1:0> initiated memory read transactions with respect to PCI-initiated memory write transactions. The three modes are shown in the following table. Value Mode Description...
Page 176 Table 7–2 (Cont.) Diagnostic Control/Status Register Field Name Type Description <14> IPTL RWC, 0 Invalidate page table lookup. This bit is set when the longword scatter-gather map entry being accessed is invalid. Bits ad<31:0> are logged in the PCI error address register, if it is not already locked.
Page 177: Pci Error Address Register
Table 7–2 (Cont.) Diagnostic Control/Status Register Field Name Type Description <6> LOST RWC, 0 Lost error. This bit is set by a 21071-DA error condition when the address register for that error is locked because of a previous error. In this case, error information for the second error is lost.
Page 178: System Bus Error Address Register
Figure 7–4 PCI Error Address Register: 0x1A0000020 31 30 08 07 06 05 04 03 02 01 00 PCI_ERR<31:0> LJ-04197.AI Table 7–3 PCI Error Address Register Field Name Type Description <31:0> PCI_ERR<31:0> PCI error. Stores the address sent out on the PCI bus ad<1:0>...
Page 179: Dummy Registers 1 Through 3
Table 7–4 System Bus Error Address Register Field Name Type Description <31:3> SYS_ERR<33:5> System bus error address. Stores the address sent on system bus sysadr<33:5> as a result of a DMA transaction. The ﬁeld logs errors indicated by the MERR, UMRD, or CMRD bits in the DCSR, and is valid only when one of these bits is set.
Page 180: Pci Base Registers 1 And 2
Table 7–5 Translated Base Registers 1 and 2 Field Name Type Description <31:9> T_BASE<32:10> Translated base. If scatter-gather mapping is disabled, T_BASE speciﬁes the base CPU address of the translated PCI address for the PCI target window. If scatter-gather mapping is enabled, T_BASE speciﬁes the base CPU address for the scatter-gather map table for the PCI target window.
Page 181: Pci Mask Registers 1 And 2
Table 7–6 (Cont.) PCI Base Registers 1 and 2 Field Name Type Description <19> WENB RW, 0 Window enable. When clear, the PCI target window is disabled and does not respond to PCI-initiated transfers. When set, the PCI target window is enabled and responds to PCI-initiated transfers that hit in the address range of the target window.
Page 182: Host Address Extension Register 1
Table 7–7 PCI Mask Registers 1 and 2 Field Name Type Description <31:20> PCI_MASK<31:20> PCI mask. This ﬁeld speciﬁes the size of the PCI target window; it is also used in the PCI-to-CPU address translation. <19:0> Reserved — 7.5.8 Host Address Extension Register 0 The host address extension register is hardcoded to zero.
Page 183: Host Address Extension Register 2: 0X1A00001C0
Table 7–8 Host Address Extension Register 1 Field Name Type Description <31:27> EADDR<4:0> RW, 0 Extension address. This ﬁeld is used as the ﬁve high-order PCI address bits (ad<31:27>) for CPU-initiated transactions to PCI memory. <26:0> Reserved — 7.5.10 Host Address Extension Register 2 The host address extension register 2 generates ad<31:24>...
Page 184: Pci Master Latency Timer Register
7.5.11 PCI Master Latency Timer Register The PCI master latency timer register deﬁnes the latency timer period. Deﬁne a nonzero value during system conﬁguration. The register is shown in Figure 7–12 and is deﬁned in Table 7–10. Figure 7–12 PCI Master Latency Timer Register: 0x1A00001E0 31 30 08 07 06 05 04 03 02 01 00 PMLC<7:0>...
Page 185: Tlb Data Registers 0 Through 7
Figure 7–13 TLB Tag Registers 0 Through 7: 0x1A0000200 to 0x1A00002E0 31 30 08 07 06 05 04 03 02 01 00 PCI_PAGE<31:13> EVAL LJ-04205.AI Table 7–11 TLB Tag Registers 0 Through 7 Field Name Type Description <31:13> PCI_PAGE<31:13> PCI page. Speciﬁes the PCI page address (tag) for the translated CPU page address in the associated TLB data register.
Page 186: Translation Buffer Invalidate All Register: 0X1A0000400
Table 7–12 TLB Data Registers 0 Through 7 Field Name Type Description <31:21> Reserved — <20:1> CPU_PAGE<32:13> RO CPU page. Bits <32:13> of the translated CPU address can be read or written through this ﬁeld. <0> Reserved — 7.5.14 Translation Buffer Invalidate All Register: 0x1A0000400 The translation buffer invalidate all register (TBIA) is write-only.
Page 187: Pci Bus
PCI bus The PCI bus is the base for the I/O subsystem. All I/O components are connected by the 32-bit, 5 V only, PCI implementation and are called PCI devices. Figure 8–1 shows a block diagram of the I/O subsystem. PCI bus 8–1...
Page 188: Pci Bus And Interfaces To The I/O Subsystem
Figure 8–1 PCI Bus and Interfaces to the I/O Subsystem To the sysBus (CPU, Memory, Bcache) PCI Host Bridge (21071-DA) PCI to Nbus Nbus Bridge PMC Adapter Module PCI to PCI Bridge PCI Bus 32 Bits 21052 Option: PCI (PMC) PCI-VME SCSI Ethernet...
Page 189: Ethernet Controller
8.1 Ethernet Controller The physical connection to the network is the Ethernet twisted-pair connector located on the front panel of the module. The Ethernet controller is based on the DECchip 21040-AA. This chip is a PCI- based Ethernet solution that keeps processor intervention in LAN control to a minimum.
Page 190: Ethernet Controller Csrs
Figure 8–2 PCI Conﬁguration Registers Device ID = 0002h Vendor ID = 1011h : 00001000 Status Command : 00001004 Class Code Rev ID : 00001008 Don't Care Latency Timer : 0000100C I/O Base Address (CBIO) : 00001010 Memory Base Address (CBMA) : 00001014 Reserved : 00001018...
Page 191: Pci Cycles
Table 8–1 Ethernet Controller CSRs Register Meaning Address CSR0 Bus mode register xxxx xx00H CSR1 Transmit poll demand xxxx xx08H CSR2 Receive poll demand xxxx xx10H CSR3 Rx list base address xxxx xx18H CSR4 Tx list base address xxxx xx20H CSR5 Status register xxxx xx28H...
Page 192: Ethernet Address
8.1.4 Ethernet Address The Ethernet ID address for the Digital Alpha VME 4 assembly is stored in an on-board SROM, a 20-pin socketed PLCC. The Ethernet controller’s ENET ROM register (CSR9) can read the SROM. Each read access initiates 8-bit serial read cycles from the ENET ROM.
Page 193: Scsi Id
8.2.2 SCSI ID The default SCSI ID is 7. You set the SCSI ID by writing the SCSI controller’s SCID register (offset 0x04). To do this, use the following console command: >>> set PKA0_HOST_ID n For example, if you enter set PKA0_HOST_ID 4, the embedded SCSI controller assumes a SCSI ID of 4.
Page 194: Scsi Control Status Registers
Figure 8–4 PCI Conﬁguration Block Device ID = 0001h Vendor ID = 1000h : 00002000 Status Command : 00002004 Class Code Rev ID : 00002008 Don't Care Latency Timer : 0000200C I/O Base Address (SCSI_IO_BASE) : 00002010 Memory Base Address (SCSI_MEM_BASE) : 00002014 Reserved : 00002028...
Page 195: Scsi Controller Csrs
Table 8–2 SCSI Controller CSRs Label Description Offset SCNTL0 SCSI Control 0 SCNTL1 SCSI Control 1 SCNTL2 SCSI Control 2 SCNTL3 SCSI Control 3 SCID SCSI Chip ID SXFER SCSI Transfer SDID SCSI Destination ID GPREG General Purpose SFBR 1st Byte Rx’ed SOCL Output Cntrl Latch SSID...
Page 196 Table 8–2 (Cont.) SCSI Controller CSRs Label Description Offset DMA Command DNAD DMA Next Add for Data 28-2B DMA SCRIPTS Pointer 2C-2F 30-33 ScratchA R/W General Purpose Scratch Pad 34-37 DMODE DMA Mode DIEN DMA Interrupt Enable DMA Watchdog Timer DCNTL DMA Control ADDER...
Page 197: Pci I/O Companion Card
8.3 PCI I/O Companion Card You can connect an optional PMC I/O companion card to the I/O module. This card contains a 21052 PCI-to-PCI bridge chip and two sets of PCI mezzanine card (PMC) connectors that allow you to add one double-width or two single-width PCI PMC modules.
Page 199: Nbus
Nbus The Nbus is a special case of an ISA bus. The Nbus is a simple 8-bit data, 16-bit address, nonmultiplexed resource bus that interfaces with the PCI bus through the Super I/O (SIO) chip (Intel 82378IB). The interface translates PCI I/O references to the Nbus into simple read and write cycles to the resources hanging off the Nbus lines, as shown in Figure 9–1.
Page 200: Sio Chip Pci Conﬁguration Space
• NVRAM • Interval timers The bottom 1 MB in PCI sparse memory space is mapped onto the Nbus for use by the ﬂash ROM. These address regions are negatively decoded and are not affected by any other PCI device that is programmed to positively decode PCI addresses. The CPU can access the Nbus devices in I/O space on a byte-by-byte basis.
Page 201: Pci Control Register
Figure 9–2 SIO Conﬁguration Block Device ID = 0484h Vendor ID = 8086h : 00004000 Status Command : 00004004 Class Code Rev ID : 00004008 Reserved : 0000400C to 0000403F PCI Control : 00004040 MEMCS# Control (not used) : 00004044 ISA Addr Decode (not used) : 00004048 : 0000404C...
Page 202: Isa Controller Recovery Timer Register
9.1.1.2 ISA Controller Recovery Timer Register The ISA controller recovery timer register (offset +4Ch) is one of two bytewide registers used as the Nbus control word. The I/O recovery mechanism in the SIO chip is used to add recovery delay between the I/O cycles originating in the PCI bus and directed to the Nbus.
Page 203: Module Display Control Register
Register CPU Address Nbus Offset Module display control 1 C001 0000 Module conﬁguration 1 C001 0020 Interrupt register 1 1 C001 0040 Interrupt register 2 1 C001 0060 Interrupt register 3 1 C001 0080 Interrupt register 4 1 C001 00A0 Memory conﬁguration 0 1 C001 00C0 Memory conﬁguration 1...
Page 204: Module Conﬁguration Register
Figure 9–3 Module Display Control Register 08 07 06 05 04 03 02 01 00 MOD_DISP_REG : Don't Care Brightness Control Display Character ML013287 The display character is stored in bits <6:0>. The most signiﬁcant bit (bit <7>) can be set to increase the brightness of the display. Figure 9–4 shows the character set of the display.
Page 205: Module Conﬁguration Register
This read-only register contains information relating to module revision, CPU speed, and SCSI options. The information read from this register is hardwired on the module and is unaffected by resets. A write of 1 to bit 0 of this register clears the Periodic Real-Time timer.
Page 206: Interrupt And Interrupt Mask Registers 1, 2, 3, 4
Table 9–2 (Cont.) Module Conﬁguration Register Field Name Type Description <6:5> CPU ID Determine the speed of the CPU according to the following table: <6:5> Deﬁnition 224 MHz 288 MHz Reserved Reserved 9.2.3 Interrupt and Interrupt Mask Registers 1, 2, 3, 4 See Chapter 11 for descriptions of these registers.
Page 207: Memory Conﬁguration Registers
These registers are read-only. The values are loaded from memory DIMMs, identiﬁed in Table 2–8 at power-up. A complete description of the memory DIMMs is in Chapter 6. Table 9–3 DIMM Identiﬁcation DIMM J# DRAM# Bank# Memory Conﬁguration Register DRAM0 refers to the DIMM array containing memory data lines 0 - 63. DRAM1 refers to the DIMM array containing memory data lines 64 - 127.
Page 208: Memory Identiﬁcation Register
Figure 9–7 Memory Identiﬁcation Register 08 07 06 05 04 03 02 01 00 MEM_ID_REG : Don't Care Bank 1 DRAM1 ID1 Bank 1 DRAM1 ID0 Bank 1 DRAM0 ID1 Bank 1 DRAM0 ID0 Bank 0 DRAM1 ID1 Bank 0 DRAM1 ID0 Bank 0 DRAM0 ID1 Bank 0 DRAM0 ID0 ML013316...
Page 209: Presence Detect
Table 9–4 Presence Detect PD Bit Description <3:0> PD 4-1 PD Bits Conﬁguration DRAM Refresh 4 3 2 1 (Parity/ECC) Organization Address Address Periods (ms) Normal Slow 0 1 0 0 1M x 72/80 1M x 4/16 0 1 0 1 2M x 72/80 1M x 4/16 1 0 1 1...
Page 210: Reset Reason Registers
Table 9–5 ID Bits ID Bit Description <6,4,2,0> ID 0 Used to deﬁne memory DIMM conﬁguration (see Table 9–6). <7,5,3,17> ID 1 Sets the refresh mode, according to the following values: Normal Self refresh Table 9–6 Memory DIMM Conﬁguration Bit Description x72 Parity x72 ECC...
Page 211: Reset Reason Registers
These registers are read/pseudowritable registers located at a ﬁxed address on Nbus in PCI I/O address space. Register 1 is located in Nbus offset 0x80A but is also aliased in two longwords at 0x80E and 0x82E. The register contains four reset status bits and one diagnostics in progress (DIP) bit. In reset reason register 3, at 0x82E, any write operation sets <4:0>.
Page 212: Heartbeat Register
Table 9–7 (Cont.) Reset Reason Registers Field Name Type Description <2> VME reset 0x80A : R/W to If set, it indicates that the module received clear a VME reset. 0x80E : Read Only 82E : R/W to set <3> Power-up 0x80A : R/W to If set, all other bits are ignored.
Page 213: Module Control Register
Figure 9–9 Module Control Register 1 08 07 06 05 04 03 02 01 00 MOD_CNTRL_REG_1 : Don't Care Timer 0 Mode Enable Undefined Watchdog Reset Enable Undefined Flash Switch Flash Write Enable Flash Select Flash Address 20 ML013289 Table 9–8 Module Control Register Field Name Type...
Page 214: Bcache Conﬁguration Register
Table 9–8 (Cont.) Module Control Register Field Name Type Description <5> Watchdog Timer When 0, watchdog timer expiration has no Reset Enable effect. If set, and the DIP bit of the reset reason register is cleared, a watchdog timer expiration generates a hardware reset of the module.
Page 215: Rom
Table 9–9 Bcache Size and Speed Decode <2> <1> <0> Bcache Size Bcache Speed Disables Bcache 512 KB 15 ns 2 MB 12 ns Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use 9.3 ROM The system has two ROM structures:...
Page 216: Super I/O Chip
Figure 9–11 Flash ROM Layout/Addressing Start of Console Firmware <00> ROM_BASE_ADDR : 512 KB Start of User Flash 512 KB <01> 1 MB <10> 1 MB <11> 1 MB ML013291 The ﬂash ROM can be rewritten. To protect the ﬂash ROM from unauthorized /accidental updates, a hardware switch must be closed before write operations are enabled.
Page 217: Super I/O Register Address Space
Channel B is uncommitted and uninitialized by system ﬁrmware. For more information about these serial lines, see Chapter 2. 9.4.2 Super I/O Register Address Space CPU Address: 0x1C0003E00 - 0x1C0007FE0 Nbus offset: 0x01F0 - 0x03FF Table 9–10 lists the base address values for the serial port and parallel port controller.
Page 218 Table 9–10 (Cont.) Super I/O Register Address Space Map Address Offset Physical Read/Write Address Register COM2 Serial Port Registers 2F8-R 0DLAB=0 1 C000 5F00 COM2 receiver buffer register 2F8-W 0DLAB=0 1 C000 5F00 COM2 transmitter holding register 2F8 0DLAB=1 1 C000 5F00 COM2 divisor latch register (LSB) 2F9 1DLAB=0 1 C000 5F20...
Page 219: Keyboard And Mouse Controller
Table 9–10 (Cont.) Super I/O Register Address Space Map Address Offset Physical Read/Write Address Register Parallel Port Registers 3BC-R/W 1 C000 7780 Data register 3BD-R 1 C000 77A0 Status register 3BE-R/W 1 C000 77C0 Control register 1 C000 77E0 None (tristate bus) Table 9–11 lists the addresses for the integrated device electronics (IDE) registers.
Page 220: Toy Clock
Table 9–12 lists the register and memory addresses for the keyboard/mouse controller. Table 9–12 Keyboard and Mouse Controller Addresses Offset Physical Address Register 60-R 1 C000 0C00 Auxiliary/keyboard data 60-W 1 C000 0C00 Command data 64-R 1 C000 0C80 Read status 64-W 1 C000 0C80 Command...
Page 221: Toy Clock Timekeeping Registers
9.6.1 TOY Clock Timekeeping Registers CPU Address: 0x1C0100000 - 0x1C01FFFE0 Nbus offset: 0x8000 - 0xFFFF Time information is contained in eight 8-bit read/write registers offset from the base address: Table 9–13 TOY Clock Timekeeping Registers Field Register Description <0:3> TOY_BASE_ADDR+00 0.00 sec <4:7>...
Page 222: Toy Clock Command Register
Field Register Description <7> TOY_BASE_ADDR+09 Enable Oscillator bit. Enables/disables the TOY clock chip’s internal oscillator. Use it to conserve the lithium source during transport, storage, or during any long period of non-use. When clear, the TOY clock operates. When set, the internal oscillator is disabled (factory default).
Page 223: Interval Timing Registers
Table 9–14 (Cont.) TOY Clock Command Register Field Name Type Description <2> Not used <3> Watchdog Timer Enable <4> Pulse/Level O/P <5> Watchdog Timer Assertion <6> Watchdog Timer Select <7> Transfer Enable Enables/disables changes to the values in the timekeeping registers. When clear, the current value in the readable registers is frozen even though the internal timing continues.
Page 224: 82C54 Control Byte
Table 9–15 Timer Interface Registers Register Field TMR_BASE_ADDR = 4000 Description <7:0> TMR_BASE_ADDR+00 Timer#0 Register TMR_BASE_ADDR+04 Timer#1 Register TMR_BASE_ADDR+08 Timer#2 Register TMR_BASE_ADDR+0C Control Register TMR_BASE_ADDR+10 Interrupt Status Register TMR_BASE_ADDR+14 Interrupt Status Register To program the timer device for initialization or during normal operation, the control byte (TMR_BASE_ADDR + 0x0C) is written.
Page 225: Interval Timing Control Register
Table 9–16 Interval Timing Control Register Field Name Type Description <7:6> Speciﬁes which timer is to be conﬁgured by this control byte. When set to ‘‘11’’, the control byte is a status read command, not a Timer Control operation. As a status read command, the control byte can be used to freeze the state of the timers for read- back.
Page 226: Timer Registers
Figure 9–14 82C54 Timer Data Access Data Rd/Wr (byte) Mode 01 or 11? Mode 11? "Signal Done" Data Rd/Wr (byte) ML013296 9.7.2 Timer Registers Each timer element is a 16-bit synchronous down counter. The device asserts or pulses the corresponding output pin when a counter reaches a 0 count. The following timers are identical in function but are fully independent: •...
Page 227: Timer Modes
interrupt request (IRQ). The IRQ can be dismissed by an access to the timer interrupt status register. 9.7.3 Timer Modes Of the six timer modes of which the 82C54 chip is capable, Digital Alpha VME 4 implements the following counting modes: Table 9–17 Timer Modes Mode Description...
Page 228 The timer output is initially high. When the timer value is written, the output is driven low. The counter decrements to 0 where it drives the output high. • Mode 1 - Hardware Retriggerable One-Shot This mode allows a value to be written to the timer that can be used when a hardware trigger has been received.
Page 229: Interrupts
9.7.4 Interrupts The expiration of timers #0 and #2 are recorded in a timer status register. The asserted state of either or both of the timer status bits can be enabled to assert an interrupt request. The active low outputs of timer #1 and #2 are routed to P2 connector pins. The active low clock and gate inputs of timer #0 are also tied to P2 connector pins.
Page 230: Timer Interrupt Status Registers
The Timer IRQ line is asserted for a low-to-high transition of a timer’s output pin when that timer is enabled in the CSR to cause an interrupt. The interrupt is held asserted until the timer status summary register is read (clear on read). The corresponding timer expiration status bit is always set by a low-to-high on the timer output but this only causes the IRQ line to be asserted if the corresponding interrupt enable bit is set.
Page 231: Watchdog Timer
Table 9–18 (Cont.) Timer Interrupt Status Register Field Name Type Description <1> Timer #2 status When clear, the IRQ is dismissed. The bit is cleared at the end of the read cycle of a read operation originating from TMR_BASE_ ADDR+14. A read operation from TMR_BASE_ ADDR+10 has no effect.
Page 232: Watchdog Timer Registers
(general-purpose registers (GPRs), and so forth) at the time the watchdog timer expires before the full hardware reset. Watchdog timer operation is controlled by four registers - three in the DS1386 chip and a single enable bit in the module control register. Operation of the watchdog timer must be conﬁgured in the TOY clock command register (TOY_ BASE_ADDR+0x0B) and enabled in the module control register (MOD_CNTRL_ REG).
Page 233: Watchdog Timer Module Control Register
Table 9–19 Watchdog Timer TOY Clock Command Register Field Name Type Description <0> Not used <1> Watchdog timer ﬂag <2> Not used <3> Watchdog timer enable <4> Pulse/level O/P <5> Watchdog timer assertion <6> Watchdog timer select <7> Transfer enable See description of TOY clock.
Page 234: Nonvolatile Ram
9.9 Nonvolatile RAM Digital Alpha VME 4 offers just under 32 KB of battery backed-up on-board SRAM. The RAM is provided by the DS1386 chip and is held nonvolatile by the built-in lithium battery source. The memory is read/write accessible in Nbus space. In effect, the DS1386 chip (TOY clock, watchdog timer, and NVRAM) contains 32 KB read/write byte elements.
Page 235: Vme Interface
VME Interface The VME interface handles the VMEbus and its interactions with the PCI bus. This chapter describes the functions of the VME interface, which are controlled by the operating system. See the documentation for the operating system for instructions on conﬁguring the VME interface. The VME interface consists of the DC7407 chip, the VIC64 chip, the CY7C964 bus interfaces, and the connectors to the VMEbus on the backplane.
Page 236: Vmebus Master
The VME interface serves the following purposes: • As a VMEbus master, it controls PCI bus-to-VMEbus, or outbound, transactions • As a VMEbus slave, it handles VMEbus-to-PCI bus, or inbound, transactions and interprocessor communication. • It can be conﬁgured as the VME system controller, handling functions such as arbitration of bus ownership.
Page 237: Mapping Window_1 And Window_2
Figure 10–2 shows a mapping of Window_1 and Window_2. Figure 10–2 Mapping Window_1 and Window_2 512 MB Window_1 64 MB Window_2 S/G 255 S/G 0 ML013378 Each page can be mapped to any one of the three VMEbus address spaces: A32, A24, or A16.
Page 238: Outbound Scatter-Gather Mapping
Figure 10–3 Mapping Pages From PCI to VME 4 GB Mem Space Scatter-Gather Mapping 2048 x 256K 512 MB Pages ML013377 10.1.1 Outbound Scatter-Gather Mapping The outbound scatter-gather entries control and map all master accesses from Digital Alpha VME 4 to the VMEbus. Figure 10–4 shows an outbound scatter- gather entry and how the VMEbus address is formed from the VME page and the PCI address.
Page 239: Outbound Scatter-Gather Entry
Figure 10–4 Outbound Scatter-Gather Entry 02 01 00 VME Addr <31:0> o/b VME Page <31:18> PCI Addr <17:2> 06 05 04 PCI Addr <28:18> o/b VME Page Function Code <2:1> Address Size <1:0> Swap <2:0> Mode Valid ML013328 A PCI memory access in either VME WINDOW_1 or VME WINDOW_2 address windows causes a lookup for the corresponding scatter-gather entry.
Page 240: Address Modiﬁer
10.1.1.1 Address Modiﬁer The scatter-gather entry has two ﬁelds that provide the address modiﬁer used in the master VMEbus transfer. The address size (ASIZ) and function code (FC) ﬁelds map directly to the VME interface controller’s input for ASIZ and FC. Table 10–1 shows the use of these ﬁelds.
Page 241: Data Transfers
The two accesses are handled as an indivisible sequence on the VMEbus by acquiring VMEbus ownership for the current access and holding it until another master operation is done by the processor. This is designed for doing atomic VMEbus RMW cycles. The VIC interface conﬁguration register must be programmed with VIC_ ICR<7:5>...
Page 242: Vic Block Transfer Control Register
Because the VMEbus speciﬁcation prohibits crossing any 256/2 KB boundaries, any DMA must split into a number of bus transfers. At the interval between these transfers, the VME interface can be programmed to wait a period of time before arbitrating again for the VMEbus and proceeding. This delay gives slave accesses to the Digital Alpha VME 4 the opportunity to complete during a block- mode transfer.
Page 243: Requesting The Vmebus
• Source address • Destination address The mapping of PCI memory to VMEbus addresses is handled as usual through the scatter-gather mapping mechanism, however, the address modiﬁers in the mapping entry are automatically transformed to generate the block-mode version of the speciﬁed address modiﬁer code (except for user-deﬁned address modiﬁer codes).
Page 244: Decoding Addresses
Incoming slave accesses are mapped and controlled by two incoming scatter- gather maps: • For A32 accesses, a Digital Alpha VME 4 system occupies up to 128 MB of memory mapped by 16384 scatter-gather entries, each mapping an 8 KB page.
Page 245: Address Decoding
VIF_ABR (VME_IF_BASE + 184) deﬁnes the base address of the Alpha VME 4 system in each VMEbus address space as shown in Figures 10–7 and 10–8. Figure 10–7 Address Decoding VME A32 Addr VME A24 Addr VME A16 Addr = Region of address which can be compared to form base address ML013341 Associated with each of the top three comparison bytes is a bit mask to control the number of bits that are checked during a VMEbus address match.
Page 246: Inbound Scatter-Gather Entries
10.2.2 Inbound Scatter-Gather Entries The inbound scatter-gather RAM format is shown in Figure 10–9 and described in Table 10–3. Figure 10–9 Inbound Scatter-Gather Entry With A32 Address Mapping 02 01 00 Memory Addr <31:0> Memory Page VME Addr <12:2> 06 05 04 VME Addr <26:13>...
Page 247: Vme Interface Processor Page Monitor Csr
Table 10–3 (Cont.) VME Address Field Name Description <13:12> Page Speciﬁes how a Digital Alpha VME 4 system checks the scatter- Monitor gather entry for access, according to the following values: No monitoring of the page. Each time the page is accessed, Monitor 1 is incremented. Each time the page is accessed, Monitor 2 is incremented.
Page 248: Interprocessor Communication
Table 10–5 VME Interface Processor Page Monitor CSR Field Name Description <2:0> Monitor 1 Number of access to page. <3> Overﬂow Overﬂow for Monitor 1. When a counter overﬂows, it sets a bit in VIP_BESR register. If enabled by the VIP_ICR register, the overﬂow causes VIP_LIRQ<0>...
Page 249: Interprocessor Communication Module Switches
Because the global switches are meant to be issued to several modules, the slave targets of a global switch access do not acknowledge the cycle, but rather the master driving the write data transfer acknowledgements (DTACKs) the cycle itself (the VIF_ABR should be set to generate a self-access by the global-switch write).
Page 250 Table 10–6 (Cont.) Interprocessor Communication Register Map Through VIF_ <byte 1>+ Register Interprocessor communication registers (ICR) 8-bit general-purpose register 3 8-bit general-purpose register 4 VIC revision register Read-only. Provides VIC64 hardware revision. VIC status register Read-only. Provides VIC64 status revision. Intercommunication register status Bits <4:0>...
Page 251: System Controller Operation
Table 10–6 (Cont.) Interprocessor Communication Register Map Through VIF_ <byte 1>+ Register Interprocessor communication module switches (ICMS) Write-only. A write to an odd address sets the switch; a Write to an even address clears that switch. Clear module switch 0 Set module switch 0 Clear module switch 1 Set module switch 1...
Page 252: Arbitrating The Vmebus
10.3.1 Arbitrating the VMEbus 10.3.1.1 Requesting the VMEbus Three arbitration schemes — priority, round-robin, and single-level — are achieved by a combination of setting the arbiter/requester conﬁguration register (VIC_ABR, offset 0xB0) and using the VMEbus request lines. See Table 10–7 and Figure 10–11.
Page 253: Releasing The Vmebus
Table 10–7 Arbiter/Requester Conﬁguration Register Field Name Description <3:0> Fairness The fairness timeout ﬁeld accepts the following values: timeout Fair request is not enabled. Non-zero Number of 2-microsecond intervals that make up the fairness timeout period. Fairness timeout period is not enabled, that is, the Digital Alpha VME 4 system can only request the VMEbus if no other requests for the VMEbus are being asserted.
Page 254: Vic Release Control Register
In addition to these four bus release modes, the scatter-gather RMW bit (RMC) can be used to force Digital Alpha VME 4 to hold ownership of the VMEbus for two accesses before releasing in the programmed ROR, RWD, or ROC fashion. See Section 10.1.2 for details.
Page 255: System Clock Output
Table 10–8 (Cont.) VIC Release Control Register Field Name Description <7:6> Release protocol Speciﬁes the release mode, according to the following values: Release-on request (ROR) the Digital Alpha VME 4 system keeps ownership until another device requests the bus. Release-when-done (RWD) the Digital Alpha VME 4 system releases the bus immediately after completion of the cycles for which it requested ownership.
Page 256: Vmebus Transfer Timers
10.3.3.2 VMEbus Transfer Timers When enabled, the VME interface starts the transfer timer whenever the data phase of a cycle is signaled (DSx* asserting). If the timer expires before the data cycle is acknowledged or completes in error, the VME interface, as the system controller, ﬂags a VMEbus error (asserting BERR*).
Page 257: Local Bus Transfer Timer
Table 10–9 (Cont.) VMEbus Transfer Timeout Register Field Name Description <7:5> VMEbus Speciﬁes the timeout, according to the following values: timeout 4 microseconds 16 microseconds 32 microseconds 128 microseconds 256 microseconds 512 microseconds Disabled 10.3.3.3 Local Bus Transfer Timer When enabled, the local bus transfer timer starts whenever a data phase is initiated on the local bus (the bus between the VIC64 and DC7407).
Page 258: Vic Interrupt Request/Status Register
Figure 10–14 VIC Interrupt Request/Status Register 08 07 06 05 04 03 02 01 00 VME_IF_BASE + 80 : Don't Care VIC_VIRSR IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 Enable(1)/Disable(0) ML013345 Table 10–10 VIC Interrupt Request/Status Register Field Name Description <0>...
Page 259: Vmebus Interrupt Vector Base Registers
Figure 10–15 VMEbus Interrupt Vector Base Registers Don't Care Status/ID Vector ML013346 A local interrupt can be generated to the CPU by the VME interface when it detects a VMEbus IACK cycle for a VME interrupt that is pending. This interrupt can be used to inform system software that the VMEbus interrupt request has been serviced.
Page 260: Byte Swapping
10.4 Byte Swapping The Digital Alpha VME 4 interface provides hardware to support byte-swapping for transfers to and from the VMEbus. Four modes of swapping are supported. The swap mode is deﬁned for each inbound or outbound page by the related scatter-gather entry.
Page 261: Vic64 Byte Swapping
Figure 10–17 Swap Modes Mode 0: No swap Mode 1: Byte swap Little Little Endian Endian Endian Endian Byte Add. Byte Add. Byte Add. Byte Add. Mode 2: Word swap Mode 3: Longword swap Little Little Endian Endian Endian Endian Byte Add.
Page 262: Swap Modes
Figure 10–18 Big Endian VME Byte Lane Formats byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 0 byte 1 byte 2 byte 3 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 1...
Page 263: Pci Be# To Local A1,0 And Siz1,0 Translation For Various Swap Modes
Table 10–13 PCI BE# to Local A1,0 and SIZ1,0 Translation for Various Swap Modes Mode 0 Mode 3 No Swap Mode 1 Mode 2 Longword A1,0 Byte Swap Word Swap Swap <3:0> SIZ1,0 A1,0 SIZ1,0 A1,0 SIZ1,0 A1,0 SIZ1,0 1111 No cycle No cycle No cycle...
Page 264: Initializing The Vme Interface
Table 10–14 Local Bus A1,0 and SIZ1,0 to PCI BE# Translation Local Bus Mode 0 Mode 1 Mode 2 Mode 3 A1,0 SIZ1,0 Data D[31:0] 0000 0000 0000 0000 D[31:8] 1000 0100 0010 0001 D[23:0] 0001 0010 0100 1000 D[15:0] 1100 1100 0011...
Page 265: Programming Scatter-Gather Ram
The windows deﬁned by these registers must not overlap each other. The following sections describe these registers and the region of address space they deﬁne. Table 10–15 Access to PCI Memory Addresses Conﬁguration Address Register Space Purpose VME_CSR_BASE 00000810 This register gives access to the DC7407, VIC64, and CY7C964 registers when the base address of a window in PCI memory space is written into the register.
Page 266: Conﬁguring The Vic64
The scatter-gather RAM is an 32K n longword page in memory space. The top 27 bits are read/write; the remaining 5 bits are MBZ. Scatter-gather RAM is not initialized by hardware and starts up in a random state. Firmware must initialize this area to a default state before using the VME subsystem.
Page 267 DMASICR Bits 2-0 Local IPL setting for end of DMA interrupt. Bits 6-3 Reserved, must read as 1s. Bit 7 End of DMA interrupt mask bit. LICR1-7 Bits 2-0 Local IPL setting for LIRQ interrupt line. Bit 3 Indicates voltage level at LIRQ pin. Bit 4 Autovector enable.
Page 268 Bits 7-2 User deﬁned. Combines with ICMS switch number to provide vector. LIVBR Bits 1-0 Read only. Bits 7-2 User deﬁned. Combines with LIRQ number to provide vector. EGIVBR Bits 1-0 Read only. Bits 7-2 User deﬁned. Combines with ﬁxed codes to provide vector. ICFSR Bits 3-0 Module switches.
Page 269 Bit 0 Set to include VMEbus acquisition time in local bus timeout. Bit 1 When VME interface is used as system controller, this bit is set to indicate arbitration timeout. Bits 4-2 Recommended timeout period for local bus is 64 µs (011). Bits 7-5 Recommended timeout period for VMEbus is 128 µs (100).
Page 270 Bits 6,5 VMEbus request level. Bit 7 Arbitration mode. AMSR Deﬁnes response top and generation of user-deﬁned address modiﬁer codes. BESR All 8 bits are ﬂags set by the VIC after status conditions that must be cleared by the processor. DMASR Bit 0 Block transfer in progress.
Page 271: Summary Of Vme Interface Registers
Bits 3-0 Interleave period. Recommend a value of 0xF. Bit 4 Data direction bit: 0=write, 1=read. Bit 5 MOVEM enable. Recommend this be clear. Bit 6 BLT with local DMA enable. Bit 7 Module based DMA transfer enable. BTLR1-0 Registers for block transfer length for local DMA block mode transfers. System reset register.
Page 272 Table 10–16 (Cont.) VME_IF_BASE + VIC_BTDR Block transfer deﬁnition register VIC_ICR Interface conﬁguration register VIC_ARCR Arbiter/requester conﬁguration register VIC_AMSR Address modiﬁer source register VIC_BESR Bus error status register VIC_DMASR DMA status register VIC_SS0CR0 Slave select 0/control register 0 The D32 enable must be set in VIC_SS0CR0. VIC_SS0CR1 Slave select 0/control register 1 VIC_SS1CR0...
Page 273: Vifabr
Table 10–16 (Cont.) VME_IF_BASE + VIP_IBISGMSK VME interface processor inbound internal scatter-gather entry mask VIP_IBISGWORD VME interface processor inbound internal scatter-gather entry control word VIP_SGCCHIX VME interface processor scatter-gather cached index VIP_SGCWRD VME interface processor scatter-gather cached control word VIP_PCIERTADR VME interface processor PCI error target address register VIP_PCIERTCBE VME interface processor PCI error target command/byte...
Page 274: Vme Subsystem Restrictions (As Of 03-Jun-94)
10.7 VME Subsystem Restrictions (as of 03-Jun-94) This section describes limitations on the use of the VME subsystem due to outstanding hardware constraints. The intention is that these will be eliminated as new revision hardware components become available. This section will be updated as restrictions change.
Page 275: System Interrupts
System Interrupts 11.1 System Interrupts Figure 11–1 shows a schematic overview of the interrupt structure in the Digital Alpha VME 4 system. Most interrupts are routed through the VIC64 chip, the Digital Alpha VME 4 interrupt controller, and the SIO chip. The 21064A receives six interrupts (CPU_IRQ[5:0]).
Page 276: Block Diagram Of The Interrupt Logic
Figure 11–1 Block Diagram of the Interrupt Logic DC7407 (VIP) VIC_IPL2 VIC_IPL1 XILINX Interrupt 21064A VIC_IPL0 CPU_IRQ3 Controller VME Reset VIPSTATUS IRQ Interrupt Priority Interval Timer IRQ VIPERROR IRQ Lines VIC64 Periodic RT Timer Timer #1 IRQ CPU_IRQ2 1 ms Heartbeat Timer VME_IRQ1 PMC0 IRQA through...
Page 277: Interrupt/Mask Register #1
Each interrupt can be individually masked by setting the appropriate bit in the interrupt/mask register. Interrupts generated by the VMEbus subsystem also need to be masked in the VIC64 chip (see Section 11.1.2). An interrupt is disabled by writing a 1 to the desired position in the interrupt/mask register. An interrupt is enabled by writing a 0.
Page 278: Vic64 Chip System Interrupt Controller
Figure 11–4 Interrupt/Mask Register #3 07 06 05 04 03 02 01 00 804 : PMC1 IRQ C PMC0 IRQ C PMC1 IRQ B PMC0 IRQ B SCSI IRQ ETHER IRQ SIO IRQ VME IPL3 ML013319 Figure 11–5 Interrupt/Mask Register #4 02 01 00 803 : Reserved...
Page 279: Basic Operation
11.1.2.1 Basic Operation The VIC64 chip handles 19 interrupt sources. Each of these can be individually programmed to any of the seven IPLs in the controller’s interrupt control registers (ICRs). The generic form of the ICR is shown in Figure 11–6. Figure 11–6 Generic ICR 08 07 06 03 02 01 00...
Page 280: Vic64 Chip Interrupt Sources
Table 11–2 VIC64 Chip Interrupt Ranking RANK Interrupt Description CSRs DC7407 Error VIC_LICR7, VIC_LIVBR VME Interface Status/Error VIC_EGICR, VIC_EGIVBR not used not used not used not used DC7407 Status VIC_LICR2, VIC_LIVBR not used Interprocessor Communications VIC_ICGSICR, VIC_ICGSIVBR Global Switch Interprocessor Communications VIC_ICMSICR, VIC_ICMSIVBR Module Switch VMEbus IRQ7*...
Page 281: Vmebus Interrupt Requests
Each of the these interrupt sources has an associated ICR that allows the interrupt to be programmed with an individual IPL or to be disabled. Figure 11–7 shows these ICRs. Figure 11–7 Device ICRs 08 07 06 03 02 01 00 Don't Care Disable Encoded Priority 1-7...
Page 282: Status/Error Interrupts
Figure 11–9 VME IRQ* ICRs 08 07 06 03 02 01 00 Don't Care Disable Encoded Priority 1-7 ML013305 Table 11–3 VME IRQ ICR Priority Assignments Address Register Line :VME_IF_BASE+04 VIC_ICR1 1RQ1 :VME_IF_BASE+08 VIC_ICR2 IRQ2 :VME_IF_BASE+0C VIC_ICR3 IRQ3 :VME_IF_BASE+10 VIC_ICR4 IRQ4 :VME_IF_BASE+14 VIC_ICR5...
Page 283: Dma Status Icr
• DMA completion • VMEbus IACK cycle in response to a VMEbus interrupt generated by an Alpha VME system These conditions are divided into three cases. The ﬁrst ‘‘case’’ is DMA completion. There is an ICR associated with this event, VIC_DMASICR (see Figure 11–10), which allows the signaling of DMA completion.
Page 284: Vic Error Group Icr
Figure 11–11 VIC Error Group ICR 08 07 06 05 04 03 02 VME_IF_BASE + 48 : Don't Care VIC_EGICR ACFAIL* Interrupt Mask Write Post Fail Interrupt Mask Arb. Timeout Interrupt Mask SYSFAIL* Interrupt Mask SYSFAIL* Asserted IPL for this group of Interrupts ML013310 Finally, a local (on-board) interrupt is generated by the VIC64 chip when the VME interface detects a VMEbus IACK cycle to itself.
Page 285: Sio Chip Programmable Interrupt Controller
Figure 11–13 VIC Error Group Interrupt Vector Base Register 08 07 06 05 04 03 02 01 00 VME_IF_BASE + 58 : Don't Care VIC_EGVIBR User Programmable Vector-Base 000 ACFail 001 Write Post Fail 010 Arb. Timeout 011 SYSFAIL 100 VMEbus IACK Received 110 DMA Completion ML013312 11.1.4 SIO Chip Programmable Interrupt Controller...
Page 286: Nmi Status And Control Register
11.1.4.2 NMI Status and Control Register Figure 11–14 shows the NMI status and control register. Figure 11–14 NMI Status and Control Register 08 07 06 05 04 03 02 01 00 Don't Care SERR # Status HALT Status Ignore on read HALT Enable SERR Enable Ignore on read...
Page 287: Epic Interrupt
Table 11–4 (Cont.) NMI Status and Control Register Bits Field Name Type Description <3> HALT Enable When set to a one, HALTs are disabled and the halt status bit in this register is cleared. When cleared (reset default), HALTs are enabled as NMI events.
Page 288 The VMEbus SYSRESET* assertion generates a module reset only if Switch 3 is closed. This prevents a module conﬁgured as a VME system controller from locking into a reset state when it issues a VME SYSRESET* under software control. If Switch 3 is open, the VIC64 chip still resets (all internal registers return to their default state, current transactions are aborted) but the module reset is not generated.
Page 289: Console Primer
Console Primer This chapter describes the Digital Alpha VME 4 console and explains how to use basic commands to perform console tasks. The console achieves much of its power and ﬂexibility from its traditional UNIX functionality. This chapter gives you an understanding of the basic functions of the UNIX like kernel, various utilities and tools, the user interface, and how these compare with the structure of the OpenVMS operating system.
Page 290: Command Overview
• Self-test diagnostics and extended functional diagnostics. You use UNIX command methods to combine these tools to solve complex problems. The UNIX command methods are piping, I/O redirection, command- level scripting, and control functions. Because the console is built around a multitasking kernel, it can support more complex functions, such as systems exercisers, the Maintenance Operations Protocol (MOP) listener, and remote console operations.
Page 291: Shell Operators
12.1.3 Shell Operators The UNIX command line makes use of some Bourne shell operators to complete a command. In OpenVMS, some commands take parameters. The shell operators are similar but are much more powerful because you can use them to combine commands.
Page 292: Using Flow Control
Table 12–2 (Cont.) Console Shell Operators Operator Name Description ( ),{} Grouping Shows which commands are grouped together in complex command lines. These operators override the [precedence] of pipe, sequence, and background operators. Form: {cmd1 ; cmd2} | cmd3 *,?,[...] Pattern speciﬁers Like OpenVMS wildcard characters.
Page 293: Getting Information About The System
• if command_sequence then command_sequence [ elif command_sequence then command_sequence ] [ else command_sequence ] ﬁ Conditional branching in if, while, and until loops is determined by the exit status of the command sequence following the control structure. In general, an exit status of zero indicates success and results in the execution of the true path.
Page 294: Getting Help
Command Description Example VMS PALcode V5.56-4, OSF PALcode X1.45-8 show pal Displays version number of PALcode show device Displays known dkb0.0.0.1.0 DKB0 RZ57 devices on system mke0.0.0.4.0 MKE0 TZ85 eza0.0.0.6.0 EZA0 08-00-2B-19-60-31 ezb0.0.0.7.0 EZB0 08-00-2B-1A-2C-06 p_a0.7.0.0.0 Bus ID 7 p_c0.7.0.2.0 Bus ID 7 pkb0.7.0.1.0 PKB0...
Page 295: Examining And Depositing To Memory Or System Registers
>>> help examine deposit NAME examine FUNCTION Display data at a specified address. SYNOPSIS examine [-{b,w,l,q,o,h,d}] [-{physical,virtual,gpr,fpr,ipr}] [-n <count>] [-s <step>] [<device>:]<address> NAME deposit FUNCTION Write data to a specified address. SYNOPSIS deposit [-{b,w,l,q,o,h}] [-{physical,virtual,gpr,fpr,ipr}] [-n <count>] [-s <step>] [<device>:]<address> <data> The help command supports a type of wildcarding.
Page 296 The examine and deposit commands manipulate devices to get access to data within the system. The default device is physical memory. When another device is speciﬁed, that device becomes the default. A default device is sticky, that is, all subsequent commands affect that device until another device is explicitly speciﬁed and becomes the new default.
Page 297: Accessing Memory
12.4.1 Accessing Memory Commands are available for gaining access to memory. Note Because the console itself and other critical data structures reside in memory, be careful not to alter them. Use the alloc command to ﬁnd an unused 1000-byte block of memory, as shown in the following example: >>>...
Page 298: Examining Registers
An alternate method for dumping memory (or other devices or ﬁles) is the hex dump command, hd. The -l option speciﬁes the number of bytes to display. Note Both -l and -n have the same result, but -l only works with hd and -n only works with examine.
Page 299 >>> e r0 # Examine R0 symbolically,... gpr: R0) 0000000000000002 >>> e gpr:0 #...explicitly as device offset,... gpr: R0) 0000000000000002 >>> e 0 ...or implicitly as device offset. gpr: R0) 0000000000000002 >>> e 8 # Examine R1... gpr: R1) 000000000000C408 >>>...
Page 300: Using Pipes And Grep To Filter Output
12.5 Using Pipes and grep to Filter Output To search for speciﬁc values in a device, use a pipe with the grep command. A pipe ( | ) enables the output of one command to be the input for the next command without creating an intermediate ﬁle.
Page 301: Running Commands In Background
>>> ls foo # Check to see if foo exists. foo no such file >>> e 3fff000 -n 1 > foo # Redirect examine output to file foo. >>> ls foo # Check to see if foo exists. >>> cat foo # Display foo.
Page 302: Killing A Process
>>> ps # Display complete process status. Pri CPU Time Affinity CPU Program State -------- -------- --- -------- -------- --- ---------- ---------------------- 0000006c 001423a0 3 2 00000001 0 ps running 0000005c 00144b40 2 19253 00000001 0 memtest ready 0000005b 00147a60 2 9 00000001 0 sh_bg waiting on 00144B40 00000059 0014c060 2...
Page 303: Copying Scripts Over The Network
To add another command to the script, use the append operator, >>. If the command you are appending contains characters that could be interpreted by the echo command, use a grouping character to enclose the appended command. The following example uses the single quote ’ grouping character to prevent the command-separator character ( ;...
Page 304 $ create sample. show version ls -l sample (Control-Z exit) 2. Make the ﬁle compatible with the MOP load protocol. To accomplish this, run the add_header.exe program to append a one-block header to the ﬁle, making it compatible with the MOP load server. This executable program is on the Firmware Update CD at [ALPHAVME]ADD_HEADER.EXE.
Page 305 >>> cat sample show version ls -l sample >>> sample version V1.1-0 Jul 1 1996 10:16:59 rwx- 512/2048 sample Console Primer 12–17...
Page 306: Digital Alpha Vme 4 Console Command Summary
Table 12–3 Digital Alpha VME 4 Console Command Summary Command Options Parameters VMS like Console Commands boot [-ﬁle ﬁlename] [-ﬂags root,bitmap] [-halt] [ boot_device ] deposit [-{b,w,l,q,o,h}] [-n val] [-s val] [ device:]address data examine [-{b,w,l,q,o,h,d}] [-n val] [-s val] [ device:]address help [command]...
Page 307 Table 12–3 (Cont.) Digital Alpha VME 4 Console Command Summary Command Options Parameters UNIX like Console Commands ﬁle... envar value sleep time sort ﬁle... [-{c | d | s}] string1 [string2] uniq ﬁle... [-{l | w | c}] ﬁle... Unique Console Commands alloc [-z heap_address] size [modulus]...
Page 308 Table 12–3 (Cont.) Digital Alpha VME 4 Console Command Summary Command Options Parameters Unique Console Commands process_id new_ priority stop device_path 12–20 Console Primer...
Page 309: Console Commands
Console Commands Console mode provides the user interface that you enter when the power-on self-test (POST) completes. The console prompt is: >>> Console mode is entered in any of the following ways: • You press the Halt/Reset switch on the front panel. Depending on your operating system and applications running at the time, this could damage application ﬁles.
Page 310: Command Line Characteristics
• Ctrl/S—Suspends output to the console terminal • Ctrl/Q—Resumes output to the console • Ctrl/C—Aborts the current command, if possible The console program has no control over this once control has been passed to another program such as an operating system or loadable diagnostic. •...
Page 311: Console Command Dictionary
13.1.4 Console Command Dictionary The following commands are supported by the Digital Alpha VME 4 console program. Console Commands 13–3...
Page 312: Alloc
alloc alloc — allocate a block of memory Exports the routine out to the shell so you can allocate a block of memory malloc from heap. You can then use the block simultaneously with several test routines (there can be several readers but only one writer). Syntax alloc size [ modulus ] [ remainder ] [-ﬂood] [-z heap_address ]...
Page 313 alloc See Also dynamic, free Console Commands 13–5...
Page 314: Boot
boot boot — bootstrap the system Initializes the processor, loads a program image from the speciﬁed boot device, and transfers control to that image. If you do not specify a boot device, the default boot device, deﬁned by the value of the BOOTDEF_DEV environment variable, is used.
Page 315 boot A 300-byte database in the same format as the BOOTP message is used to store the received packet. Once a BOOTP packet is broadcasted and received, the database is marked as initialized, ending the ﬁrst stage of the operation. 2.
Page 316 boot The ﬁle name deﬁned by this environment variable becomes the ﬁle name in the outgoing BOOTP request packet. For example: >>> set ewa0_bootp_file /var/adm/ris/ris0.alpha/vmunix.old 5. Do not specify a ﬁle name: >>> boot ewa0 With this method, because none of the environment variables are written, the boot process runs through both stages.
Page 317 boot Environment Variable Field Description EWA0_INETADDR Internet address Local address. TFTP and the Address of the network Resolution Protocol (ARP) do not interface (EWA0) operate properly without the correct address. EWA0_SINETADDR Internet address of The address of a server, which may the remote server or may not be on the local network.
Page 318 boot EWA0_DEF_SINETADDR EWA0_DEF_GINETADDR EWA0_DEF_SUBNETMASK EWA0_DEF_INETFILE These variables are deﬁned in the following example: >>> set EWA0_DEF_INETADDR 16.123.16.53 >>> set EWA0_DEF_SINETADDR 16.123.16.242 >>> set EWA0_DEF_GINETADDR 16.123.16.242 >>> set EWA0_DEF_SUBNETMASK 255.255.255.0 >>> set EWA0_DEF_INETFILE bootfiles/vmunix >>> set EWA0_INET_INIT nvram Another way for the database to be initialized is when BOOTP is invoked, either explicitly or as a consequence of invoking TFTP.
Page 319 boot Protocol Drivers You normally use BOOTP and TFTP to bootstrap across a network. However, you can invoke the protocols as protocol drivers. The BOOTP and TFTP protocols must be followed by a network in the protocol tower. When a BOOTP request is broadcast, the environment variable EWA0_BOOTP_ SERVER is copied into the sname ﬁeld of the request packet and the variable EWA0_BOOTP_FILE is copied into the ﬁle ﬁeld of the request packet.
Page 320 boot Arguments boot_device A device path or list of devices from which the ﬁrmware attempts to boot, or a saved boot speciﬁcation in the form of an environment variable. Use the set command with the environment variable BOOTDEF_DEV to deﬁne the default boot device.
Page 321 boot >>> boot -fi //usr//local//bootfile//alphavme_v1_1-0 -protocol bootp ewa0 The system performs a TCP/IP BOOTP network boot from Ethernet port EWA0. >>> boot -flags 0,1 The system boots from the default boot device using boot ﬂag settings 0,1. >>> boot -halt dka0 The system loads the operating system from the SCSI disk, , but remains dka0...
Page 322: Break
break break — break from a program loop Breaks from a for, while, or until loop. Exits the current shell with a status or returns the status of the last command. Syntax break [ break_level ] Arguments break_level Speciﬁes the status code to be returned by the shell. Example >>>...
Page 323: Cat
cat — copy ﬁles Concatenates ﬁles that you specify to the standard output. If you do not specify ﬁles on the command line, the cat command copies standard input to standard output. You can also copy or append one ﬁle to another by specifying I/O redirection. Syntax cat [-l length ] ﬁle1 [ ﬁle2 .
Page 324: Chmod
chmod chmod — change ﬁle attributes Changes the speciﬁed attributes of a ﬁle. The chmod command is a subset of the equivalent UNIX command. Syntax {r,w,x,b,z} ﬁle1 [ ﬁle2 . . . ] chmod Arguments ﬁle1 [ ﬁle2 . . . ] Speciﬁes the ﬁles or inodes to be modiﬁed.
Page 325 chmod Examples >>> chmod +x script Adds the executable attribute to the ﬁle, script >>> chmod =r errlog Sets the ﬁle to read only. errlog >>> chmod -w dk* Makes all SCSI disks nonwriteable. See Also chown, ls -l Console Commands 13–17...
Page 326: Chown
chown chown — change ownership of memory block Changes the ownership of a memory block to the speciﬁed process. Syntax chown pid address1 [ address2 . . . ] Arguments Speciﬁes the hexadecimal process identiﬁer (PID) of the new owner. You can display PIDs with the ps command.
Page 327: Clear
clear clear — delete environment variable Deletes an environment variable from the name space. Note Some environment variables, such as BOOTDEF_DEV, are permanent and cannot be deleted. Syntax clear variable_name Arguments variable_name Speciﬁes the name of the environment variable to be deleted. Example >>>...
Page 328: Clear_Log
clear_log clear_log — clear error log in NVRAM Clears and initializes the area of NVRAM used for console error logging. The entire area of NVRAM where fault information is stored is cleared to zero. Miscellaneous pointers, counters, and initialization ﬂags used in the error logging process are reset accordingly.
Page 329: Date
date date — display or change time Displays or modiﬁes the current date and time. If you include no arguments, the command displays the current date and time. If you do include arguments, the command modiﬁes the current date and time stored in the time-of-year (TOY) clock.
Page 330 date Example >>> date 199208031029.00 >>> date 10:29:04 August 3, 1992 >>> 13–22 Console Commands...
Page 331 deposit deposit — write memory data Writes data to a memory location, a register, a device, or a ﬁle. After initialization, if you have not speciﬁed a data address or size, the default address space is physical memory, the default data size is a quadword, and the default address is zero.
Page 332 deposit fpr: Floating-point register set. The data size defaults to quadword. The following symbols for address are recognized: f0, f1, . . . f31. ipr: Internal processor register set. The size defaults to quadword. The following symbols for address are recognized: ps, asn, asten, astsr, at, fen, ipir, ipl, mces, pcbb, prbr, ptbr, scbb, sirr, sisr, tbchk, tbia, tbiap, tbis, esp, ssp, usp, and whami.
Page 333 deposit Names the location immediately following the last location referenced in an examine or deposit. For references to physical or virtual memory, the location is the last address plus the size of the last reference. For other address spaces, the address is the last address referenced plus one.
Page 334 deposit -physical The address space is physical memory. Using this option is the same as specifying device. pmem: -virtual The address space is virtual memory. Using this option is the same as specifying device. vmem: -gpr The address space is general purpose registers. Using this option is the same as specifying the device.
Page 335 deposit >>> d -l -n 10 -s 200 pmem:0 8 Deposits 8 into the ﬁrst longword of each of the ﬁrst 17 pages in physical memory. See Also examine Console Commands 13–27...
Page 336 dynamic dynamic — show memory Shows the state of dynamic memory. Dynamic memory is split into two main heaps: the console’s private heap and the remaining memory heap. Syntax dynamic [-c [-r]] [-h] [-p] [-v] [-setsize] [-extend byte_count ] [-z heap_address ] Options Performs a consistency check on the default heap or the heap speciﬁed with option -z.
Page 337 dynamic Examples >>> dynamic zone zone used used free free utili- high address size blocks bytes blocks bytes zation water -------- ---------- ------- ---------- ------- ---------- ------- ---------- 00097740 1048576 358944 689664 34 % 371872 001D2B80 14805504 14805504 >>> dynamic -cv -z 97740 zone zone used...
Page 338: Echo
echo echo — display text output Sends a line of text that you enter on the command line to the current output device. The default output device is your console screen. The echo command separates arguments (words) in the line with blanks and adds a new line character to the end of the line.
Page 339 echo >>> echo > foo ’this is the simplest way _>to create a long file. All characters will be echoed _>to file foo until the closing single quote.’ >>> cat foo this is the simplest way to create a long file. All characters will be echoed to file foo until the closing single quote.
Page 340: Eval
eval eval — evaluate expression Evaluates a postﬁx expression. Syntax eval operand1 operand2 operator Arguments operand1 The ﬁrst numeric value to be evaluated. operand2 The second numeric value to be evaluated. operator One of the following: • + Add the operands. •...
Page 341 eval Displays the output as binary values. Displays the output as octal values. Displays the output as decimal values. Displays the output as hexadecimal values. Examples >>> eval 5 10 + The sum of 5 plus 10 is 15. >>> eval -ix -d 5 10 + The sum of 5 plus 0x10 is 21 (decimal).
Page 342 examine examine — display memory data Displays data located at a speciﬁed address: a memory location, a register, a device, or a ﬁle. After initialization, if you have not speciﬁed a data address or size, the default address space is physical memory, the default data size is a quadword, and the default address is zero.
Page 343 examine vmem: Virtual memory. All access and protection checking occur. If the access would not be allowed to a program running with the current PS, the console issues an error message. If memory mapping is not enabled, virtual addresses are equal to physical addresses. gpr: General purpose register set, R0-R31.
Page 344 examine ipr- name Names an internal processor register. The size defaults to quadword; the address space defaults to ipr. The following symbols for name are recognized: ps, asn, asten, astsr, at, fen, ipir, ipl, mces, pcbb, prbr, ptbr, scbb, sirr, sisr, tbchk, tbia, tbiap, tbis, esp, ssp, usp, and whami.
Page 345 examine The data size is octaword. The data size is hexaword. The data displayed is the decoded macro instruction. Alpha instruction decode (-d) does not recognize machine-speciﬁc PAL instructions. -physical The address space is physical memory. Using this option is the same as specifying pmem: device.
Page 346 examine >>> e -g 0 gpr: R0) 0000000000000002 Examine GPR register R0 by address space (-gpr option). >>> e gpr:0 gpr: R0) 0000000000000002 Examine R0 by device name. >>> examine pc gpr: 0000000F ( PC) FFFFFFFC Examine the program counter (PC). >>>...
Page 347: Deposit
examine >>> examine pmem: 20040048 DB MFPR S^#2B,B^48(R1) Look at the next instruction. See Also deposit Console Commands 13–39...
Page 348: Exer
exer exer — exercise devices Exercises one or more devices by performing read, write, and compare operations. Optionally, reports performance statistics. A read operation reads from a device into a buffer. A write operation writes from a buffer to a device. A comparison operation compares the contents of the two buffers.
Page 349 exer -eb end_block Speciﬁes the ending block number (hexadecimal) within the ﬁle stream. The default is 0. -p pass_count Speciﬁes the number of passes to run the exerciser. If you specify 0, the exerciser runs forever or until you enter Ctrl/C. The default is 1. -l blocks Speciﬁes the number of blocks (hexadecimal) to exercise.
Page 350 exer Write without lock from buffer1 Write without lock from buffer2 Compare buffer1 with buffer2 Seek to ﬁle offset prior to last read or write First, seek to a random block offset within the speciﬁed range of blocks. Next, call the program to create each of a set of numbers once.
Page 351 exer Description Exercises one or more devices. As described in the preceding overview section, the exer command uses two buffers, buffer1 and buffer2. The buffers are in main memory in the memory zone heap. Both buffer1 and buffer2 are initialized to a data pattern before any I/O operations occur.
Page 352 exer You can use a random number generator to seek to varying device locations before performing either a read or write operation. Randomization is achieved by calling the function , which uses a linear congruential generator (LCG) to random generate the numbers. This algorithm is not truly random, but it comes closest to meeting the needs of the exer command.
Page 353 exer The exer command returns an error code immediately after a read, write, or compare error, if the D_HARDERR environment variable is set to HALT. When an error occurs and on error is speciﬁed, then subsequent continue loop operations speciﬁed by the action string option occur except for comparisons. For instance, if a read error occurs, a subsequent comparison is skipped since a read failure preceding a compare operation guarantees that the comparison fails.
Page 354 exer >>> exer -eb 64 -bc 4 -a ’?w-Rc’ dka0 A destructive write test over block numbers 0 through 100 on disk dka0 . The packet size is 2048 bytes. The action string speciﬁes the following sequence of operations: 1. Set the current block address to a random block number on the disk between 0 and 97.
Page 355 exer >>> set myd 0 >>> exer -bs 1 -bc a -l a -a ’w’ -d1 ’myd myd ~ =’ foo >>> clear myd >>> hd foo -l a 00000000 ff 00 ff 00 ff 00 ff 00 ff 00 ..Use an environment variable myd as a counter.
Page 356 exer See Also memexer 13–48 Console Commands...
Page 357: Exit
exit exit — exit current shell Exits the current shell with the speciﬁed status or returns the status of the last command executed. Syntax exit exit_value Arguments exit_value Speciﬁes the status code to be returned by the shell. Examples >>> exit Exits returning the status of the previously executed command.
Page 358: False
false false — return failure status Returns a failure status. Syntax false Example >>> while false ; do echo foo; done >>> 13–50 Console Commands...
Page 359: Free
free free — deallocate memory Frees a block of memory that has been allocated from a heap. The block is returned to the appropriate heap. Syntax free address1 [ address2 . . . ] Arguments address1 address2 . . . Speciﬁes an address (hexadecimal) or list of addresses of allocated blocks to be returned to the heap.
Page 360: Grep
grep grep — search for regular expressions Globally searches for regular expressions and prints any lines containing occurrences of the regular expressions. A regular expression is a shorthand way of specifying a wildcard type of string comparison. Since the grep command is line oriented, it only works on ASCII ﬁles.
Page 361 grep Repeated matching. When placed after a pattern, the plus sign indicates that the pattern should match one or more times. For example, [0-9]+ matches any sequence of one or more digits. Optional matching. When placed after a pattern, the question mark indicates that the pattern can match zero or one times.
Page 362 grep >>> alloc 20 00FFFFE0 >>> deposit -q pmem:fffff0 0 >>> e -n 3 ffffe0 pmem: FFFFE0 EFEFEFEFEFEFEFEF pmem: FFFFE8 EFEFEFEFEFEFEFEF pmem: FFFFF0 0000000000000000 pmem: FFFFF8 EFEFEFEFEFEFEFEF >>> e -n 3 ffffe0 | grep -v 0000000000000000 pmem: FFFFE0 EFEFEFEFEFEFEFEF pmem: FFFFE8 EFEFEFEFEFEFEFEF pmem: FFFFF8 EFEFEFEFEFEFEFEF...
Page 363 hd — dump ﬁle contents Dumps the contents of a ﬁle in hexadecimal and ASCII format. Syntax [-{byte | word | long | quad}] ﬁle... Arguments ﬁle... Speciﬁes the ﬁles to be displayed. Options -byte Prints data in bytes. -word Prints data in words.
Page 364 >>> -word foo 00000000 6874 2065 7571 6369 206B 7262 776F 206E the quick brown 00000010 6F66 2078 756A 706D 6465 6F20 6576 2072 fox jumped over 00000020 6874 2065 616C 797A 6420 676F the lazy dog >>> -long foo 00000000 20656874 63697571 7262206B 206E776F the quick brown 00000010 20786F66 706D756A 6F206465 20726576...
Page 365: Help
help help— help on commands Deﬁnes and shows the syntax for each command that you specify on the command line. If you do not specify a command, the help command displays information about itself and lists the commands for which additional information is available. For each argument (or command) on the command line, the help command tries to ﬁnd all topics that match that argument.
Page 366 help >>> help * # List all topics and associated text. Requests help on all topics. >>> help ex Requests help on all commands that begin with ‘‘ex’’. >>> help boot Requests help on the boot command. 13–58 Console Commands...
Page 367: Init_Ev
init_ev init_ev — initialize environment variables Sets all environment variables to their default values. Once you issue this command, you need to reset the system or issue the init command to set the environment variables to their default values. Syntax init_ev Example >>>...
Page 368: Initialize
initialize initialize — initialize the console, a device, or the processor Initializes the console, a device, or the processor. Syntax init[ialize] [-c] [-d device ] Options Speciﬁes that the console be initialized. -d device Speciﬁes a device to be initialized. Examples >>>...
Page 369: Kill
kill kill — delete process Deletes the processes listed on the command line. Processes are killed by making a call to a kernel function with the process ID (PID) as the argument. Syntax kill pid1 [ pid2 . . . ] Arguments pid1 pid2 .
Page 370: Line
line line — read a line Copies one line (up to a new line) from the standard input channel of the current process to the standard output channel of the current process. This command always writes at least a new line as output. Use this command in scripts to read from the user’s terminal, or to read lines from a pipeline while in a loop.
Page 371 ls — list ﬁles Lists ﬁles or inodes in the system. Inodes are RAM disk ﬁles, open channels, and some drivers. RAM disk ﬁles include script ﬁles, diagnostics, and executable shell commands. Syntax ls [-l] [ ﬁle1 ] [ ﬁle2 . . . ] Arguments ﬁle1 ﬁle2 .
Page 372: Memexer
memexer memexer — memory exerciser Starts a speciﬁed number of graycode memory test processes running in the background. Each test randomly allocates and tests blocks of memory twice the size of the Bcache, using all available memory. The pass count is 0 to run the tests forever.
Page 373 memtest memtest — memory test Tests memory with any or all of four tests: Test Description Graycode memory test Writes, reads, and veriﬁes a graycode pattern and an inverse graycode pattern for the speciﬁed address range. March memory test Writes, reads, and veriﬁes a marching pattern and an inverse marching pattern for the speciﬁed address range.
Page 374 memtest 2. Reads each location, veriﬁes the data, and writes the inverse of the data. The read-verify-write is done one longword at a time. This causes the following: • All data bits are written as a one and zero. • All but one data bit toggle between longword writes.
Page 375 memtest The random test: 1. Obtains an address index into the Linear Congruential Generator (LCG) structure that is dependent on the speciﬁed length. The test obtains the data index as a function of the entered random data seed and the maximum 32 bit data pattern.
Page 376 memtest If you issue a Ctrl/C or the kill command with a PID in the middle of testing, process might not abort right away. To increase speed of execution, memtest check for a Ctrl/C or kill command done outside of any test loops. If this is not satisfactory, you can run concurrent processes in the background with memtest...
Page 377 memtest -rs random_seed Speciﬁes the random seed. Use this option only with the -rb option. The default is 0. Speciﬁes to randomly allocate and test all of the speciﬁed memory address range. Allocations are done of block_size. Speciﬁes fast mode. If you specify -f, the data comparison is omitted. Only ECC /EDC errors are detected.
Page 378 memtest Speciﬁes a group name. Currently, the only group supported is MFG. Speciﬁes a soft error threshold. Examples >>> memtest -sa 200000 -l 1000 Tests memory starting at 0x200000 (-sa) for 0x1000 bytes (-l). >>> memtest -sa 200000 -l 1000 -f Tests memory from 0x200000 for 0x1000 bytes, but data is not veriﬁed (-f).
Page 379 memtest See Also memexer Console Commands 13–71...
Page 380: Net
net — MOP function Using a speciﬁed port, performs basic maintenance operations protocol (MOP) operations. The net command performs basic MOP operations, such as, loopback, request IDs, and remote ﬁle loads. The net command also provides the means to observe the status of a network port.
Page 381 Sends an Ethernet loopback to a speciﬁed destination node. You specify the address of the destination node with the -da option. Requests a MOP loopback. Requests to be rebooted by sending a MOP V4 request boot message to a remote boot node.
Page 382 -lw wait_in_secs Waits the speciﬁed number of seconds for the loop messages from the -l1 option to return. If the messages do not return in the speciﬁed time period, an error message is generated. -sv mop_version Sets the preferred MOP version number for operations. Valid values are 3 or 4. Examples >>>...
Page 383 ps — show process Displays the system state in the form of process status and statistics. Syntax Example >>> ps Pri Time Affinity CPU Program State -------- -------- --- ------ -------- --- --------- ---------------------- 0000008f 0010e8a0 3 0 00000001 0 ps running 00000020 00110160 1 0 ffffffff 0...
Page 384: Pwrup
pwrup pwrup — run power-on diagnostics Runs the power-on diagnostics script. The pwrup command initializes network environment variables and runs memory tests. Syntax pwrup Example >>> pwrup Runs the power-on script. 13–76 Console Commands...
Page 385 rm — remove ﬁle Removes the speciﬁed ﬁles from the ﬁle system. Allocated memory is returned to the heap. Syntax rm ﬁle1 [ ﬁle2 . . . ] Arguments ﬁle1 ﬁle2 . . . Speciﬁes the ﬁles to be deleted. Example >>>...
Page 386 sa — set process afﬁnity Changes the afﬁnity mask of a process. The afﬁnity mask of a process speciﬁes the processors on which the process can run. Syntax sa process_id afﬁnity_mask Arguments process_id Speciﬁes the process ID (PID) of the process to be modiﬁed. afﬁnity_mask Speciﬁes the new afﬁnity mask, which indicates on which processors the process can run.
Page 387: Semaphore
semaphore semaphore — show system semaphores Shows all the semaphores known to the system by traversing the semaphore queue. Syntax semaphore Example >>> semaphore Name Value Address First Waiter -------------------------------- -------- -------- ------------------------ dyn_sync 00000001 00050378 dyn_release 00000001 000503A0 shell_iolock 00000001 0015D684 exit_iolock 00000001 0015D770 grep_iolock 00000001 0015DB20 eval_iolock 00000001 0015DC0C...
Page 388: Set
set — set environment variable Sets or modiﬁes the value of an environment variable. Some of the environment variables are stored in nonvolatile memory. You use environment variables to pass conﬁguration information between the console and the operating system. For a listing of predeﬁned environment variables, see Table 3–2. Syntax set envar_name value [-default] [-integer] [-string] Arguments...
Page 389 the factory to the device that contains the factory-installed software. For systems that do not ship with factory-installed software, the default setting is null. boot_ﬁle Sets the ﬁle name to be used when a bootstrap requires a ﬁle name. The default setting is null.
Page 390 >>> set AUTO_ACTION BOOT Sets the system’s default console action to boot after an error, halt, or power-on. >>> set BOOT_FILE avme.sys Sets the ﬁle name to be used when the system’s boot requires a ﬁle name to avme.sys >>> set BOOT_OSFLAGS 0,1 Sets the system’s default boot ﬂags to 0,1.
Page 391: Set Led
set led set led — display char on LED Displays a character on the front panel light emitting diode (LED). Syntax set led char [-b] Arguments char Speciﬁes the character to display on the front panel LED. Preﬁx metacharacters with a backslash (\). Options Speciﬁes that the character be displayed in bright mode.
Page 392: Set Reboot Srom
set reboot srom set reboot srom — set reboot mode to Serial ROM Mini-Console Enters the Serial ROM (SROM) Mini-Console. The only valid (and necessary) argument is srom. When you issue this command, you enter the SROM Mini-Console the next time you reset or power on the system.
Page 393: Set Toy Sleep
set toy sleep set toy sleep — disable TOY clock’s internal oscillator Disables the DS1386 TOY clock’s internal oscillator, lengthening the shelf life of the device. When you execute this command, bit 8 of the MONTH register of the device is set to 1, disabling the TOY clock’s oscillator. The TOY clock’s time registers cease to advance, and the life of the device’s internal lithium battery is lengthened.
Page 394 sh — create new shell Creates another shell process. Each shell process implements most of the functionality of the Bourne shell. Syntax " [-l] [-r] [-p] [arg . . . ] Arguments Speciﬁes a text string terminated with white space. Options Prints lines as they are read.
Page 395 Example >>> sh # start a new shell >>> # the new shell’s prompt >>> sh -v <foo # execute command file "foo" and show lines as read in >>> sh -x <foo # print out commands as they are executed and after >>>...
Page 396: Show
show show — display system information Displays the current value of an environment variable or other system parameter. Syntax show [{conﬁg, device, hwrpb, led, map, mode, pal, version}] [ envar_name ] Arguments conﬁg Displays the system conﬁguration. device Displays devices and controllers in the system. hwrpb Displays the Alpha hardware restart parameter block (HWRPB).
Page 397 show Commonly Used Environment Variables auto_action Displays the console action following an error halt or power on. The action can be halt, boot, or restart. bootdef_dev Displays the device or device list from which bootstrapping is attempted. boot_ﬁle Displays the ﬁle name to be used when a bootstrap requires a ﬁle name. boot_osﬂags Displays the additional parameters to be passed to system software.
Page 398: Show Conﬁg
show conﬁg show conﬁg — display system conﬁguration Displays the system conﬁguration. Syntax show conﬁg Example >>> show config Digital Equipment Corporation Alpha VME 4/288 SRM Console V1.1-0 VMS PALcode V5.56-4, OSF PALcode X1.45-8 MEMORY: 16 Meg of system memory System Controller: VIC64 Enabled Hose 0, PCI...
Page 399: Show Device
show device show device — displays devices Displays the devices and controllers in the system. By default, all devices and controllers that respond are shown. The device naming convention is as follows. dka0.0.0.0.0 | || | | | | | || | | | +-- Hose # : Always zero for Digital Alpha VME 4 | || | | +---- Slot # : On PCI System = <PCI bus * 1000>+<PCI function * 100>+<PCI slot>...
Page 400 show device >>> show device e ewa0.0.0.6.0 EWA0 08-00-2B-1D-27-AA Displays devices that start with ‘‘e’’. >>> show device *k* # Show SCSI devices. dkc0.0.0.2.0 DKC0 RZ57 mke0.0.0.4.0 MKE0 TLZ04 Displays all devices with ‘‘k’’ in the device name. >>> show device dk # Show SCSI disks.
Page 401: Show Hwrpb
show hwrpb show hwrpb — display HWRPB Displays the address of the Alpha hardware restart parameter block (HWRPB). Syntax show hwrpb Example >>> show hwrpb HWRPB is at 2000 >>> Console Commands 13–93...
Page 402: Show Led
show led show led — display LED character Displays the current character being displayed on the front LED panel. Syntax show led [-hex] Options -hex Displays the contents of the LED register. If you do not specify -hex, the character being displayed is echoed to the console. Examples >>>...
Page 403: Show Map
show map show map — display memory map Displays the current system virtual memory map. Note The map is empty after all console initialization. To ﬁll in the page table entries, enter the boot command with the -halt option at the console prompt.
Page 404: Show_Log
show_log show_log — display NVRAM error log information Displays console-detected fault information that was previously stored in the error log area of NVRAM. If you do not specify command-line options, the command displays the most recent fault. Console error logging is completely independent of the operating system’s error logging.
Page 405 show_log >>> show_log -n 3 =============================== F A U L T #1 ================================ Time of Error: 13:10:06 9-AUG-1994 Machine Check: IOC Controller SCB Vector : 67 IOC Status 0 : 0400031604000316 IOC Status 1 : 0400000004000000 : 0000000000064c40 =============================== F A U L T #2 ================================ Time of Error: 13:08:39 9-AUG-1994 Diagnostic : Interval Timer...
Page 406: Sleep
sleep sleep — suspend execution Suspends execution of a console process for a speciﬁed number of seconds. The console process temporarily wakes up every second to check for and kill pending bits. Syntax sleep [-v] time_in_secs Arguments time_in_secs Speciﬁes the number of seconds to sleep. The default is one second. Options Speciﬁes that the value supplied is in milliseconds.
Page 407: Sort
sort sort — sort a ﬁle Arranges the lines of a ﬁle in lexicographic order and writes the results to STDOUT. The size of the ﬁle that sort can handle is limited by the size of memory. Syntax sort ﬁle Arguments ﬁle Speciﬁes the ﬁle to be sorted.
Page 408 sp — set priority Modiﬁes the priority of a process. Changing the priority of the process impacts the behavior of the process and the rest of the system. Syntax sp process_id new_priority Arguments process_id Speciﬁes the process ID (PID) of the process to be modiﬁed. new_priority Speciﬁes the new priority for the process.
Page 409: Start
start start — start program Starts program execution at the speciﬁed address or starts drivers. Syntax start [-drivers [ device_preﬁx ]] [ address ] Arguments address Speciﬁes the PC address at which to start execution. Options -drivers [ device_preﬁx ] Speciﬁes the name of the device or device class to stop.
Page 410: Stop
stop stop — stop CPU or device Stops the CPU or a speciﬁed device. Syntax stop [-drivers [ device_preﬁx ]] [ processor_num ] Arguments processor_num Speciﬁes the processor to stop. If you use this argument, specify 0. Options -drivers [ device_preﬁx ] Speciﬁes the name of the device or the device class to stop.
Page 411: Update
update update — update ﬂash ROMs on the system Loads new ﬁrmware into the ﬂash ROMs (FEPROMs). To modify the ﬂash ROMs, you must close DIP switch #2 on the Digital Alpha VME 4 module. The update process proceeds as follows: 1.
Page 412 update -target device Speciﬁes the device that contains the FEPROMs to be upgraded. Valid targets are CONSOLE and USERFLASH. Examples >>> update -fi alphavme_v1_1-0 -dev ewa0 -prot mop -tar console update -path mop:alphavme_v1_1-0/ewa0 -target console ..Network load complete. Host name: OHMY Host address: aa-00-04-00-00-4b new: 1.1-0 Note: Module DIP Switch #2 must be CLOSED to enable Updates!
Page 413 update The program will take at most several minutes. Erasing the target flash device... Erasure completed. Programming... Programming completed Verifying... Update successful >>> The example above shows how to do an update using the TFTP protocol. Console Commands 13–105...
Page 415: A Module Connector Pinouts
Module Connector Pinouts Sections A.1 through Section A.5 provide pinout information for the Alpha VME • CPU connector • I/O Type 1 card connector • Primary breakout module connector • Secondary breakout module connector • PMC I/O Companion card A.1 CPU Connector Pinouts The Alpha VME 4 CPU (54-24325-xx) J12 (P2) connector has the following power/ground pin assignments: Row A...
Page 416: Vmebus (J1) Connector Pinouts
A.2.1 VMEbus (J1) Connector Pinouts Table A–1 lists the pinouts for the VMEbus (J1) connector (P2). Table A–1 VMEbus (J1) Connector Row A Row B Row C SCSI_DATA0_L MSDATA SCSI_DATA1_L Ground MSCLK SCSI_DATA2_L Ground SCSI_DATA3_L VME_A24 KBDATA SCSI_DATA4_L VME_A25 KBCLK SCSI_DATA5_L VME_A26 WD_STATUS_OC...
Page 417: Console (J6) And Serial (J7) Connector Pinouts
Table A–1 (Cont.) VMEbus (J1) Connector Row A Row B Row C VME_D28 PP_PE Ground VME_D29 PP_BUSY Ground VME_D30 PP_ACK_L Ground VME_D31 PP_AFD_L Ground PP_INIT_L PP_SLIN_L A.2.2 Console (J6) and Serial (J7) Connector Pinouts Table A–2 lists the pinouts for the console (J6) and serial (J7) connectors. Figure A–1 shows a pinout diagram.
Page 418: Ethernet (J9) Connector Pinouts
A.2.3 Ethernet (J9) Connector Pinouts Table A–3 lists the pinouts for the Ethernet (J9) connector. Figure A–2 shows a pinout diagram. Table A–3 Ethernet (J9) Connector Pinouts Signal transmit + transmit - receive + no connection no connection receive - Figure A–2 Ethernet (J9) Connector Pinouts Pin 1 Pin 8...
Page 419 Table A–4 (Cont.) Primary Breakout Module Connector Pinouts Row A Row B Row C SCSI_DATA4_L KBCLK SCSI_DATA5_L WD_STATUS_OC SCSI_DATA6_L BREAKOUT0 SCSI_DATA7_L BREAKOUT1 SCSI_DP_L Ground SCSI_ATN_L EXT_RESET_L SCSI_BSY_L TMR2_EXT_OP_L SCSI_ACK_L Ground TMR1_EXT_OP_L SCSI_RST_L TMR_MINOR_IP_L SCSI_MSG_L TRM_MAJOR_IP_L SCSI_SEL_L Ground SCSI_CD_L PP_STB_L SCSI_REQ_L PP_ERR_L SCSI_IO_L PP_DATA0...
Page 420: Secondary Breakout Module Connector Pinouts
Figure A–3 Primary Breakout Module Connector Pinouts Side 1 J2 (SCSI) Side 2 MLO-013551 A.4 Secondary Breakout Module Connector Pinouts Figure A–4 shows the layout of the pinouts for the secondary breakout module. Note the positions of the J1 (keyboard and mouse) and J6 (parallel port) connectors.
Page 421: Keyboard And Mouse (J1) Connector Pinouts
Figure A–4 Secondary Breakout Module Connector Pinouts MLO-013552 Sections A.4.1 and A.4.2 provide more detail on the J1 and J6 connectors, respectively. A.4.1 Keyboard and Mouse (J1) Connector Pinouts Table A–5 lists the pinouts for the keyboard and mouse (J1) connector. Figure A–5 shows a pinout diagram.
Page 422: Parallel Port (J6) Connector Pinouts
Table A–5 Keyboard and Mouse (J1) Connector Signal MOUSE_DATA KBRD_DATA Ground MOUSE_CLOCK KBRD_CLOCK Figure A–5 Keyboard and Mouse (J1) Pinouts Front view mating side MLO-013553 A.4.2 Parallel Port (J6) Connector Pinouts Table A–6 lists the pinouts for the parallel port (J6) connector. Figure A–6 shows a pinout diagram.
Page 423: Pmc I/O Companion Card Connector Pinouts
Table A–6 (Cont.) Parallel Port (J6) Connector PP_DATA7 PP_ACK_L PP_BUSY PP_PE PP_SLCT PP_AFD_L PP_ERR_L PP_INIT_L PP_SLIN_L 18-25 Ground Figure A–6 Parallel Port (J6) Connector Pinouts Front view mating side MLO-013554 A.5 PMC I/O Companion Card Connector Pinouts Tables A–7 and Table A–8 list the pinouts for the PMC I/O Companion Card (54-24665-01) mouse (J2) and keyboard (J3) connectors, respectively.
Page 424: Pmc I/O Companion Card Mouse (J2) And Keyboard (J3) Connector Pinouts
Table A–7 PMC I/O Companion Card Mouse (J2) Connector Signal MOUSE_DATA KBRD_DATA Ground MOUSE_CLOCK KBRD_CLOCK Table A–8 PMC I/O Companion Card Keyboard (J3) Connector Signal KBRD_DATA MOUSE_DATA Ground KBRD_CLOCK Figure A–7 PMC I/O Companion Card Mouse (J2) and Keyboard (J3) Connector Pinouts Front view mating side MLO-013553...
Page 425: Index
Index Addresses (cont’d) physical, decoding of by PCI host bridge, 7–2 ACFAIL* assertion, 11–8 stepping in conﬁguration cycles, 7–7 Address mapping, 5–1 VME interface, decoding, 10–10 Address modiﬁer, 10–6 alloc command, 13–4 Address space Alpha VME CPU cacheable, 5–4 See Digital Alpha VME 4 DECchip 21071-CA CSR, 5–4 Arbitration timeout, 11–8 DECchip 21071-DA, 7–7...
Page 426 Cache (cont’d) BOOTED_FILE environment variable, size, tag enable values of, 6–17 3–4 Cacheable address space, 5–4 BOOTED_OSFLAGS environment cat command, 13–15 variable, 3–4 Character set, display, 9–6 BOOTP, 13–6 CHAR_SET variable, 3–4 BOOT_DEV environment variable, 3–4 chmod command, 13–16 BOOT_FILE environment variable, 3–4 chown command, 13–18 BOOT_OSFLAGS environment variable, Circuit board module etch, testing, 4–10...
Page 427 Commands (cont’d) Commands (cont’d) exit, 13–49 sa, 13–78 false, 13–50 semaphore, 13–79 free, 13–51 set, 13–80 grep, 13–52 set led, 13–83 hbeat_diag, 4–9 set reboot srom, 13–84 hd, 13–55 set toy sleep, 13–85 help, 13–57 sh, 13–86 i8254_diag show, 13–88 with -t 1, 4–10 show conﬁg, 13–90 with -t 2, 4–11...
Page 428 Connector pinouts (cont’d) Control/status registers (CSRs) (cont’d) I/O Type 1 card, A–1 PCI host bridge, 7–9 keyboard and mouse, A–7 address space of, 7–7 parallel port, A–8 SCSI controller, 8–8 PMC I/O companion card, A–9 Counters, 9–25 primary breakout module, A–4 secondary breakout module, A–6 addresses VMEbus, A–2...
Page 429 Diagnostic commands DECchip 21040-AA, 8–3 nicsr_diag (cont’d) See also Ethernet controller with -t 2, 4–17 DECchip 21071-BA, 6–1 with -t 3, 4–17 block diagram of, 6–30 niil_diag, 4–16 DECchip 21071-CA, 6–1 vip_diag block diagram, 6–2 with -t 1, 4–28 CSR address space, 5–4, 6–8 with -t 2, 4–28 functions, 6–3 with -t 3, 4–28...
Page 430 Diagnostics (cont’d) Digital Alpha VME 4 (cont’d) NCR810 internal loopback test, 4–25 power supply current and dissipation, NCR810 interrupt test, 4–26 1–4 NCR810 PCI conﬁguration register processor, 1–2 test, 4–24 product description, 1–1 NVRAM address-on-address test, 4–19 resetting, 11–13 NVRAM march I test, 4–18 SCSI-2, 1–2 NVRAM march II test, 4–19 serial and parallel interfaces, 1–2...
Page 431 D_OPER environment variable, 3–5 EWA0_DEF_GINETADDR environment D_PASSES environment variable, 3–5 variable, 3–5 D_REPORT environment variable, 3–5 EWA0_DEF_INETADDR environment D_SOFTERR environment variable, 3–5 variable, 3–5 D_STARTUP environment variable, 3–5 EWA0_DEF_INETFILE environment D_TRACE environment variable, 3–5 variable, 3–5 EWA0_DEF_SINETADDR environment variable, 3–6 EWA0_INET_INIT environment variable, echo command, 13–30 3–6...
Page 432 i8254_diag command (cont’d) with -t 6, 4–14 Identiﬁcation (ID) bits, 9–11 Inbound scatter-gather entry, 10–12 General control register, 6–11 Global switches, 10–14 Indicators, front panel Global timing register, 6–27 description, 3–2 grep command, 13–52 ﬁgure, 3–1 using pipe with, 12–12 initialize command, 13–60 init_ev command, 13–59 Installation, 2–6 to 2–27...
Page 433 Interval timing registers, 9–25 ioclrlock command, 7–6 iogrant signal, 7–6 Master DMA transfer, 10–9 memexer command, 13–64 bus controller recovery timer register, Memory, 1–2, 6–1 9–4 accessing data in, 12–9 clock divisor register, 9–4 address of, 6–1 bits, testing, 4–7 cache, 2–12 conﬁguration registers of, 9–8 Jumpers...
Page 434 NCR810 (cont’d) memtest command, 13–65 internal loopback test, 4–25 Merge buffer, memory, 6–31 interrupt test, 4–26 MODE environment variable, 3–6 PCI conﬁguration register test, 4–24 dependence of diagnostic tests on, 4–7 SCSI controller chip Modes testing, 4–24 block data transfer, 10–7 ncr810_diag command continuous, square wave output (3), with -t 1, 4–24...
Page 435 PCI bus (cont’d) primary address space of, 5–8 conﬁguration cycles to targets of, Operating system, booting, 3–7 5–9 > operator, 12–12 scatter-gather map Operators address for, 5–19 redirection operator, 12–12 page table entry in memory for, shell, 12–3 5–18 Order numbers, 2–35 translation to system bus address, 5–21 secondary, address space of, 5–8...
Page 436 PCI mezzanine card adapter, 8–11 Primary PCI bus PCI-to-physical memory addressing, 5–15 address space of, 5–8 PD bits, 9–10 decoding conﬁguration addresses Performance, 1–2 in, 5–8 Physical addresses, decoding of by PCI Printer, attaching, 2–4 host bridge, 7–2 Process, killing, 12–14 Physical speciﬁcations, 1–2, 1–4 Processor, 1–2 Pinouts, A–1...
Page 437 Registers Registers (cont’d) PCI bus (cont’d) dummy registers, 7–15 mask registers, 7–17 error and diagnostic status register, master latency timer register, 6–13 7–20 error high address register, 6–19 presence detect error low address register, 6–18 low-data register, 6–20 examining, 12–7 presense detect general control register, 6–11 high-data register, 6–21...
Page 438 Registers Scatter-gather map VIC (cont’d) address for, 5–19 local interrupt vector base register, page table entry in memory for, 5–18 11–7 translation to system bus address, register, testing, 4–28 5–21 release control register, 10–20 Scatter-gather mapping VIP PCI conﬁguration register outbound, 10–4 testing, 4–28 Scatter-gather RAM...
Page 439 System bus (cont’d) show led command, 13–94 arbitration on, 6–4 show map command, 13–95 buffering transactions of, 7–3 show_log command, 13–96 controller, 6–1, 6–4 Signal, iogrant, 7–6 error address register, 7–14 Single mode data transfers, 10–7 interface of, 6–4 SIO chip interface to, 7–2 See Super I/O chip System clock, 10–17, 10–21...
Page 440 Timers (cont’d) VIC (cont’d) VMEbus arbitration, 10–21 release control register, 10–20 VMEbus timeout, 10–21 write post failure, 11–8 VMEbus transfer, 10–22 VIC64 chip, 9–29 3 timers loopback test, 4–11 byte swapping for, 10–27 Timing register A, 6–25 conﬁguring, 10–32 Timing register B, 6–26 interrupt controller, 11–4 interrupt ranking for, 11–5 data registers, 7–21...
Page 441 VME interface (cont’d) VME_A16_BASE environment variable, registers, summary of, 10–37 3–7 restrictions, 10–40 VME_A24_BASE environment variable, scatter-gather entry, outbound, 10–4 3–7 scatter-gather mapping, outbound, VME_A24_SIZE environment variable, 10–4 3–7 single mode data transfers, 10–7 VME_A32_BASE environment variable, tests, 4–28 3–7 VME interrupt request interrupt control VME_A32_SIZE environment variable, registers, 11–7...

This manual is also suitable for:

Digital alpha vme 4/288

DEC Digital Alpha VME 4/224 User Manual

Preface

1 Product Overview

2 Installation Procedures

3 Operating the Digital Alpha VME 4 Computer

4 Diagnostics

5 System Address Mapping

6 Cache and Memory Subsystem

7 PCI Host Bridge

8 PCI Bus

9 Nbus

Quick Links

Troubleshooting

Related Manuals for DEC Digital Alpha VME 4/224

Summary of Contents for DEC Digital Alpha VME 4/224