DEC Digital Alpha VME 4/224 User Manual page 14

6-20 Refresh Timing Register: 0x180000220 . . . . . . . . . . . .
Block Diagram of the DECchip 21071-BA . . . . . . . . . .
6-21
7-1 PCI Host Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21071-DA Block Diagram . . . . . . . . . . . . . . .
7-2
7-3 Diagnostic Control/Status Register: 0x1A0000000 . . . .
7-4 PCI Error Address Register: 0x1A0000020 . . . . . . . . .
7-5 System Bus Error Address Register: 0x1A0000040 . . .
7-6 Translated Base Registers 1, 2: 0x1A00000C0,
0x1A00000E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Base Registers 1 and 2: 0x1A0000100,
7-7
0x1A0000120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-8 PCI Mask Registers 1 and 2: 0x1A0000140,
0x1A0000160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-9 Host Address Extension Register 0: 0x1A0000180 . . . .
Host Address Extension Register 1: 0x1A00001A0 . . .
7-10
7-11 Host Address Extension Register 2: 0x1A00001C0 . . .
PCI Master Latency Timer Register: 0x1A00001E0 . . .
7-12
7-13 TLB Tag Registers 0 Through 7: 0x1A0000200 to
0x1A00002E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-14 TLB Data Registers 0 Through 7: 0x1A0000300 to
0x1A00003E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus and Interfaces to the I/O Subsystem . . . . . . .
8-1
8-2 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . .
DECchip 21040-AA CSR9 (ENET ROM Register) . . . .
8-3
8-4 PCI Configuration Block . . . . . . . . . . . . . . . . . . . . . . .
Nbus and Nbus Resources . . . . . . . . . . . . . . . . . . . . . .
9-1
9-2 SIO Configuration Block . . . . . . . . . . . . . . . . . . . . . . .
Module Display Control Register . . . . . . . . . . . . . . . . .
9-3
9-4 Display Character Set . . . . . . . . . . . . . . . . . . . . . . . . .
9-5 Module Configuration Register . . . . . . . . . . . . . . . . . . .
9-6 Memory Configuration Registers 0-3 . . . . . . . . . . . . . .
9-7 Memory Identification Register . . . . . . . . . . . . . . . . . .
9-8 Reset Reason Registers . . . . . . . . . . . . . . . . . . . . . . . .
9-9 Module Control Register 1 . . . . . . . . . . . . . . . . . . . . . .
9-10 Bcache Configuration Register . . . . . . . . . . . . . . . . . . .
9-11 Flash ROM Layout/Addressing . . . . . . . . . . . . . . . . . .
TOY Clock Command Register . . . . . . . . . . . . . . . . . . .
9-12
9-13 82C54 Control Byte . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiv
6-29
6-30
7-1
7-2
7-10
7-14
7-14
7-15
7-16
7-17
7-18
7-18
7-19
7-20
7-21
7-21
8-2
8-4
8-6
8-8
9-1
9-3
9-6
9-6
9-7
9-9
9-10
9-13
9-15
9-16
9-18
9-24
9-26