Dma Status Icr - DEC Digital Alpha VME 4/224 User Manual

• DMA completion
• VMEbus IACK cycle in response to a VMEbus interrupt generated by an
Alpha VME system
These conditions are divided into three cases.
The first ''case'' is DMA completion. There is an ICR associated with this
event, VIC_DMASICR (see Figure 11–10), which allows the signaling of DMA
completion. If enabled, an interrupt is generated at the programmed IPL upon
DMA completion.
Figure 11–10 DMA Status ICR
31
VME_IF_BASE + 20 :
VIC_DMASICR
Disable
Encoded Priority 1-7
The second case is a grouping that encompasses the SYSFAIL assertion,
arbitration timeout, write posting failure, and ACFAIL conditions. The ICR
(VIC_EGICR) associated with this group (see Figure 11–11) is different than the
ICRs already discussed. Here, a single IPL is assigned for all of the events, while
the higher order register bits (<7:4>) allow individual conditions to be selectively
disabled.
08 07 06
Don't Care
System Interrupts 11–9
03 02 01 00
ML013309