DEC Digital Alpha VME 4/224 User Manual page 437

Registers (cont'd)
dummy registers, 7–15
error and diagnostic status register,
6–13
error high address register, 6–19
error low address register, 6–18
examining, 12–7
general control register, 6–11
general interrupt control register,
11–5
global timing register, 6–27
HAXR0 register, 5–5
HAXR2 register, 5–5
heartbeat, 9–14
host address extension registers, 7–18
interrupt mask registers, 9–8, 11–3
interrupt registers, 9–8
interval timing control register, 9–26
interval timing registers, 9–25
ISA
bus controller recovery timer
register, 9–4
clock divisor register, 9–4
LDx_L
high address register, 6–20
low address register, 6–19
memory
configuration registers, 9–8
control registers, 6–20
identification register, 9–8
module
clear heartbeat register, 4–9
configuration register, 9–6
control register, 9–14
display control register, 9–5
module registers, 9–4
nonmaskable interrupt status and
control register, 11–12
PCI bus
base register, 5–15
base registers, 7–16
configuration registers, 8–3, 8–7
control register, 9–3
error address register, 7–13
mask register, 5–15
Registers
PCI bus (cont'd)
mask registers, 7–17
master latency timer register,
7–20
presence detect
low-data register, 6–20
presense detect
high-data register, 6–21
refresh timing register, 6–28
reset reason registers, 9–12
SCSI controller CSRs, 8–8
summary of VME interface registers,
10–37
system bus error address register,
7–14
tag enable register, 6–16
timer
interface registers, 9–25
interrupt status registers, 9–32
registers, 9–28
timing register A, 6–25
timing register B, 6–26
TLB
data registers, 7–21
tag registers, 7–20
TOY clock
command register, 9–24
registers, testing, 4–20
timekeeping registers, 9–23
translated
base registers, 7–15
translated PCI base, 5–15
translation buffer invalidate all
register, 7–22
VIC
arbiter/requester configuration
register, 10–18
block transfer control register,
10–8
error group interrupt control
register, 11–9
error group interrupt vector base
register, 11–10
interrupt request/status register,
10–23
Index–13