Requesting The Vmebus; Vmebus Slave - DEC Digital Alpha VME 4/224 User Manual

• Source address
• Destination address
The mapping of PCI memory to VMEbus addresses is handled as usual through
the scatter-gather mapping mechanism, however, the address modifiers in the
mapping entry are automatically transformed to generate the block-mode version
of the specified address modifier code (except for user-defined address modifier
codes).
The following sequence of steps set up a master DMA:
1. Write the DMA transfer length to the VME byte length registers, VIC_
BTLR0, VIC_BTLR1. PCI deferred writes can be enabled to decouple the
CPU from the holdups on the ''local-bus'' when setting up DMAs. D64 block
mode operations are distinguished by a write to bit 4 of the VIC64's block
transfer definition register (BTDR).
2. Write the DMA direction bit (read/write) and DMA enable bit to the VIC block
transfer control register (VIC_BTCR).
3. Write to the desired PCI memory address (that will map to the target
VMEbus address) with the required PCI start address as the write data.
4. Clear the DMA enable bit in the VIC_BTCR.
5. Wait for completion notification. The completion interrupt is enabled in the
VIC status register (VIC_DMAICR) and its vector is generated by the VIC
error group interrupt vector address register (VIC_EGIVBR).

10.1.3 Requesting the VMEbus

When Digital Alpha VME 4 acts as the VMEbus master, the VME interface
must request ownership of the bus. Controlling the manner and level of the
bus request is achieved using the VIC arbiter/requester configuration register
(VIC_ARCR), shown in Figure 10–11. See Section 10.3.1 for information about
this register and VMEbus arbitration.

10.2 VMEbus Slave

The VME interface responds to A32, A24, and A16 accesses. A32 and A24 cycles
are used to access the memory of a Digital Alpha VME 4 system's memory.
Incoming A32 and A24 transactions are mapped to 8 KB pages by the VME
interface's inbound scatter-gather maps. A16 cycles provide access to a small
number of byte-wide interprocessor communication registers.
VME Interface 10–9