Host Address Extension Register 1; Host Address Extension Register 2; Host Address Extension Register 0: 0X1A0000180; Host Address Extension Register 1: 0X1A00001A0 - DEC Digital Alpha VME 4/224 User Manual

Table 7–7 PCI Mask Registers 1 and 2
Field Name
<31:20> PCI_MASK<31:20>
<19:0> Reserved
7.5.8 Host Address Extension Register 0
The host address extension register is hardcoded to zero. A read transaction from
this register returns zero; a write transaction has no effect. The register is shown
in Figure 7–9.
Figure 7–9 Host Address Extension Register 0: 0x1A0000180
31 30 29
Hardcoded to Zero

7.5.9 Host Address Extension Register 1

The host address extension register 1 generates ad<31:27> on CPU-initiated
transactions addressing PCI memory space. The register is shown in Figure 7–10
and is defined in Table 7–8.
Figure 7–10 Host Address Extension Register 1: 0x1A00001A0
31 30 29
EADDR<4:0>
MBZ
7–18 PCI Host Bridge
Type Description
RW PCI mask. This field specifies the size of
the PCI target window; it is also used in the
PCI-to-CPU address translation.
MBZ —
28 27 26 25 24 23 22 21 20 19 18 17 16
28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04201.AI
LJ-04202.AI