Tlb Data Registers 0 Through 7; Tlb Tag Registers 0 Through 7: 0X1A0000200 To 0X1A00002E0; Tlb Data Registers 0 Through 7: 0X1A0000300 To 0X1A00003E0; Tlb Tag Registers 0 Through - DEC Digital Alpha VME 4/224 User Manual

Figure 7–13 TLB Tag Registers 0 Through 7: 0x1A0000200 to 0x1A00002E0
31 30 29
PCI_PAGE<31:13>
EVAL
MBZ
Table 7–11 TLB Tag Registers 0 Through 7
Field Name
<31:13> PCI_PAGE<31:13>
<12> EVAL
<11:0> Reserved

7.5.13 TLB Data Registers 0 Through 7

The TLB data registers contain the CPU page address associated with the PCI
page address in the TLB tag registers. The registers are shown in Figure 7–14
and are defined in Table 7–12.
Figure 7–14 TLB Data Registers 0 Through 7: 0x1A0000300 to 0x1A00003E0
31 30 29
MBZ
CPU_PAGE<32:13>
MBZ
28 27 26 25 24 23 22 21 20 19 18 17 16
Type Description
RO PCI page. Specifies the PCI page address
(tag) for the translated CPU page address in
the associated TLB data register.
RO Entry valid. The entry valid bit can be read
and written through this bit. Normally, the
invalid bit contains the value read during a
page table entry read transaction.
MBZ —
28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PCI Host Bridge 7–21
LJ-04205.AI
LJ-04206.AI