DEC Digital Alpha VME 4/224 User Manual page 17

3-1 Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . .
Environment Variable Summary . . . . . . . . . . . . . . . . .
3-2
4-1 Console Diagnostic Tests . . . . . . . . . . . . . . . . . . . . . . .
System Bus Address Space Description . . . . . . . . . . . .
5-1
5-2 PCI Sparse I/O Space Byte Enable Generation . . . . . .
5-3 PCI Configuration Space Definition . . . . . . . . . . . . . . .
5-4 PCI Address Decoding for Primary Bus Configuration
Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5 PCI Sparse Memory Space Byte Enable Generation . .
PCI Target Window Enables . . . . . . . . . . . . . . . . . . . .
5-6
5-7 PCI Target Address Translation-Direct Mapped . . . .
Scatter-Gather Map Address . . . . . . . . . . . . . . . . . . . .
5-8
6-1 CSR Register Addresses for DECchip 21071-CA . . . . .
General Control Register . . . . . . . . . . . . . . . . . . . . . . .
6-2
6-3 Error and Diagnostic Status Register . . . . . . . . . . . . .
6-4 Cache Size Tag Enable Values . . . . . . . . . . . . . . . . . . .
6-5 Maximum Memory Tag Enable Values . . . . . . . . . . . . .
6-6 Configuration Register for Banks 0 and 1 . . . . . . . . . .
6-7 Timing Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-8 Timing Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-9 Global Timing Register . . . . . . . . . . . . . . . . . . . . . . . .
6-10 Refresh Timing Register . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21071-DA CSR Addresses . . . . . . . . . . . . . . .
7-1
7-2 Diagnostic Control/Status Register . . . . . . . . . . . . . . .
PCI Error Address Register . . . . . . . . . . . . . . . . . . . . .
7-3
7-4 System Bus Error Address Register . . . . . . . . . . . . . . .
Translated Base Registers 1 and 2 . . . . . . . . . . . . . . . .
7-5
7-6 PCI Base Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . .
PCI Mask Registers 1 and 2 . . . . . . . . . . . . . . . . . . . .
7-7
7-8 Host Address Extension Register 1 . . . . . . . . . . . . . . .
Host Address Extension Register 2 . . . . . . . . . . . . . . .
7-9
7-10 PCI Master Latency Timer Register . . . . . . . . . . . . . . .
7-11 TLB Tag Registers 0 Through 7 . . . . . . . . . . . . . . . . . .
7-12 TLB Data Registers 0 Through 7 . . . . . . . . . . . . . . . . .
8-1 Ethernet Controller CSRs . . . . . . . . . . . . . . . . . . . . . .
8-2 SCSI Controller CSRs . . . . . . . . . . . . . . . . . . . . . . . . .
9-1 PCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3-4
4-3
5-3
5-7
5-8
5-9
5-13
5-16
5-18
5-20
6-9
6-12
6-14
6-17
6-18
6-23
6-25
6-27
6-28
6-29
7-7
7-10
7-14
7-15
7-16
7-16
7-18
7-19
7-19
7-20
7-21
7-22
8-5
8-9
9-3
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