Table 9–4 Presence Detect
Bit
PD Bit
Description
<3:0>
PD 4-1
PD Bits
4 3 2 1
0 1 0 0
0 1 0 1
1 0 1 1
1 0 1 1
<4>
PD 5
Controls data mode access, according to the following values:
PD5
0
1
<6:5>
PD 7-6
Controls speed, according to the following values:
PD 7
0
1
1
0
0
<7>
PD 8
Used to define memory DIMM configuration (see Table 9–6).
Configuration
DRAM
(Parity/ECC)
Organization
1M x 72/80
1M x 4/16
2M x 72/80
1M x 4/16
4M x 72
4M x 4
4M x 80
4M x 4
Definition
Fast page
Fast page with EDO
PD 6
Speed
1
80 ns
0
70 ns
1
60 ns
0
50 ns
1
40 ns
RE
CE
Refresh
Address
Address
Periods (ms)
Normal Slow
10
10
16
10
10
16
12
11
64
12
10
64
Nbus 9–11
128
128
256
256