DEC Digital Alpha VME 4/224 User Manual page 270

Bits 6,5 VMEbus request level.
Bit 7 Arbitration mode.
AMSR Defines response top and generation of user-defined address modifier
codes.
BESR All 8 bits are flags set by the VIC after status conditions that must be
cleared by the processor.
DMASR
Bit 0 Block transfer in progress. Once set, must be cleared by processor.
Bit 1 LBERR during DMA transfer.
Bit 2 BERR during DMA transfer.
Bit 3 Local bus error.
Bit 4 VMEbus BERR.
Bits 5,6 Reserved, read as 1s.
Bit 7 Master write post information stored in CYs.
SS0CR0
Bits 1-0 Accelerated transfer mode. Must be set to binary 10.
Bits 3,2 Must be binary 01 for A24 slave selection.
Bit 4 D32 enable. Must be set in the Digital Alpha VME 4 system.
Bit 5 Supervisor access.
Bits 7,6 Periodic timer enable. Must be binary 00.
SS0CR1 Local bus timing values. Must be 0x00.
SS1CR0
Bits 1-0 Must be set to binary 10, accelerated transfer mode.
Bits 3,2 Must be binary 00 for A32 slave selection.
Bit 4 D32 enable. Must be set.
Bit 5 Supervisor access.
Bit 6 VIC/CY master write posting enable. Recommend this be clear.
Bit 7 Slave write post enable. Must be clear.
SS1CR1 Local bus timing values. Must be 0x00.
RCR
Bits 5-0 Block transfer burst length.
Bits 7,6 VMEbus release mode.
BTCR
10–36 VME Interface