Host Address Extension Register 2: 0X1A00001C0 - DEC Digital Alpha VME 4/224 User Manual

Table 7–8 Host Address Extension Register 1
Field Name
<31:27> EADDR<4:0>
<26:0> Reserved
7.5.10 Host Address Extension Register 2
The host address extension register 2 generates ad<31:24> on CPU-initiated
transactions addressing PCI I/O space. It also generates ad<1:0> during PCI
configuration read and write transactions. The register is shown in Figure 7–11
and is defined in Table 7–9.
Figure 7–11 Host Address Extension Register 2: 0x1A00001C0
31 30 29
EADDR<7:0>
MBZ
CONF_ADDR<1:0>
Table 7–9 Host Address Extension Register 2
Field Name
<31:24> EADDR<7:0>
<23:2> Reserved
<1:0> CONF_ADDR<1:0>
Type Description
RW, 0 Extension address. This field is used as the
five high-order PCI address bits (ad<31:27>)
for CPU-initiated transactions to PCI
memory.
MBZ —
28 27 26 25 24 23 22 21 20 19 18 17 16
Type Description
RW, 0 Extended address. Used as the eight high-
order PCI address bits ad<31:24> for CPU-
initiated transactions to PCI I/O space.
MBZ —
RW, 0 Configuration address. Used as the two
low-order PCI address bits ad<1:0> for CPU-
initiated transactions to PCI configuration
space.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PCI Host Bridge 7–19
LJ-04203.AI