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DIGITAL Semiconductor 21174 Core Logic Chip
the configuration and operating frequencies, the PCI bus supports up to 264-MB/s
(33 MHz, 64-bit) peak throughput. The PCI provides parity on address and data
cycles. Three physical address spaces are supported:
•
32-bit memory space
•
32-bit I/O space
•
256-byte-per-agent configuration space
The bridge from the 21164 system bus to the 64-bit PCI bus is provided by the 21174
chip. It generates the required 32-bit PCI address for 21164 I/O accesses directed to the
PCI. It also accepts 64-bit double address cycles and 32-bit single address cycles. How-
ever, the 64-bit address support is subject to some constraints. Refer to Appendix A for
more information on 64-bit addressing constraints.
4.2.4 Saturn-IO (SIO) Chip
The 82378ZB SIO chip provides the bridge between the PCI bus and the ISA bus.
The SIO incorporates the logic for the following:
•
A PCI interface (master and slave)
•
An ISA interface (master and slave)
•
Enhanced 7-channel DMA controller that supports fast DMA transfers and
scatter-gather, and data buffers to isolate the PCI bus from the ISA bus
•
PCI and ISA arbitration
•
A 14-level interrupt controller
•
A 16-bit basic input/output system (BIOS) timer
•
Three programmable timer counters
•
Nonmaskable interrupt (NMI) control logic
•
Decoding and control for utility bus peripheral devices
•
Speaker driver
Refer to Intel document 82420/82430 PCIset ISA and EISA Bridges for additional
information.
Functional Description
4–6
22 January 1998 – Subject To Change
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