DEC Digital Alpha VME 4/224 User Manual page 89

• See the Intel 8254 interval timer sheet for more details.
Timer 2 Square Wave Test
This test exercises timer 2. In the Digital Alpha VME 4 design, the gate input for
timer 2 is always enabled and the clock input is connected to a 10 MHz (100 ns
period) clock source.
Timer 2 is programmed to mode 3, square wave mode. After the timer is initially
programmed for mode 3 and then loaded with a count value, the OUT output
produces a continuous, square wave output whose period is equal to the count
value multiplied by the period of the clock input. The count values are chosen
such that they check stuck NDATA lines.
The event of OUT transitioning from low to high should generate a CPU
interrupt, provided the timer 2 interrupt enable bit is set.
The ISR invoked due to the timer generated interrupt increments an interrupt
counter and sets a global flag indicating the interrupt took place and that
software was dispatched to the correct point. The test verifies that the
interrupt count is within a certain range, based on the count value the timer
was programmed with and the duration of time that interrupts were enabled.
Console Command: i8254_diag -t 2
Miscellaneous Notes
• The interrupt enable bits for timers 0 and 2 (bits 4 and 5 of the interrupt
status register at address 0x4010) are not directly writable. Bit 4 is toggled
by writing to address 0x4010; bit 5 is toggled by writing to address 0x4014.
In both cases, the data written is Don't Care.
• A read of the interrupt status register at address 0x4014 causes both
interrupt status bits (bits 0 and 1) to be cleared.
• Due to hardware limitations on interrupt detection, the value programmed
into timer 2 must be greater than 2.
• See the Intel 8254 interval timer sheet for more details.
3 Timers Loopback Test
This test exercises timer 2, timer 1, and timer 0. In the Digital Alpha VME 4
design, the gate input for timer 2 and timer 1 is always enabled and the clock
input is connected to a 10 MHz (100 ns period) clock source. Timer 0 accepts its
input through a P2 loopback connector to which the outputs of timers 1 and 2 are
tied. Timer 2 is the gate input and timer 1 provides the clock.
Interval Timer Tests
Diagnostics 4–11