Bank Set 0 Timing Register A: 0X180000C00 - DEC Digital Alpha VME 4/224 User Manual

The description of the parameters also indicates the corresponding DRAM
parameter. Bank 0's timing register A is shown in Figure 6–17 and is defined
in Table 6–7.
Figure 6–17 Bank Set 0 Timing Register A: 0x180000C00
MBZ
S0_RDLYCOL
S0_RDLYROW
S0_COLHOLD
S0_COLSETUP
S0_ROWHOLD
S0_ROWSETUP
Table 6–7 Timing Register A
Field Name
<15> Reserved
<14:12> S0_RDLYCOL
<11:9> S0_RDLYROW
<8:7> S0_COLHOLD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Type Description
MBZ —
RW, 1 Read delay from column address. Used only
when starting in page mode. Delay from
column address to latching first valid read
data.
P rogrammed value
RW, 1 Read delay from row address. Delay from
row address to latching first valid read data.
P rogrammed value
RW, 1 Column hold (t
assertion. Used to determine when the
current column address can be changed to
the next column or row address.
P rogrammed value
Cache and Memory Subsystem 6–25
ML013278
desired value
= 2 .
desired value
= 4 .
) from b0_cas<1:0>_l
CAH
desired value
= 1 .
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