Interrupt/Mask Register #1; Interrupt/Mask Register #2 - DEC Digital Alpha VME 4/224 User Manual

Each interrupt can be individually masked by setting the appropriate bit in the
interrupt/mask register. Interrupts generated by the VMEbus subsystem also
need to be masked in the VIC64 chip (see Section 11.1.2). An interrupt is disabled
by writing a 1 to the desired position in the interrupt/mask register. An interrupt
is enabled by writing a 0. The interrupt/mask register is write only.
A read of the interrupt/mask register returns the state of the interrupts
regardless of which mask bits are set. A 1 means that the interrupt source
has asserted an interrupt.
Figure 11–2 Interrupt/Mask Register #1
802 :
Reserved
IMS Heartbeat Timer
VME IPL5
Periodic Heartbeat Timer
Interval Timer
VME IPL6
VME Reset
Figure 11–3 Interrupt/Mask Register #2
803 :
Reserved
PMC1 IRQA
PMC0 IRQA
VME IPL4
07 06 05 04 03 02 01 00
ML013317
07 03 02 01 00
ML013318
System Interrupts 11–3