DEC Digital Alpha VME 4/224 User Manual page 13

2-15 Connecting the PMC I/O Companion Card . . . . . . . . . .
Installing the PMC I/O Companion Card . . . . . . . . . . .
2-16
3-1 Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . .
Loopback Descriptions for Interval Timer Test 3 and
4-1
4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 LAN Address ROM Format . . . . . . . . . . . . . . . . . . . . .
4-3 SROM Test Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console POST Flows . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4
4-5 Console POST Flows . . . . . . . . . . . . . . . . . . . . . . . . . .
System Bus Address Map . . . . . . . . . . . . . . . . . . . . . .
5-1
5-2 PCI Sparse I/O Space Address Translation . . . . . . . . .
PCI Memory Space Address Translation . . . . . . . . . . .
5-3
5-4 PCI Target Window Compare Scheme . . . . . . . . . . . . .
Scatter-Gather Map Page Table Entry in Memory . . . .
5-5
5-6 Scatter-Gather Map Translation of PCI Bus Address to
System Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1 Cache and Memory Subsystem . . . . . . . . . . . . . . . . . .
Address and Data Paths of Cache and Memory . . . . . .
6-2
6-3 21071-CA Block Diagram . . . . . . . . . . . . . . . . . . . . . . .
Cache Subsystem for a 2 MB Cache . . . . . . . . . . . . . . .
6-4
6-5 Maximum and Minimum DIMM Bank Layouts . . . . . .
General Control Register: 0x180000000 . . . . . . . . . . . .
6-6
6-7 Error and Diagnostic Status Register:
0x180000020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-8 Tag Enable Register: 0x180000060 . . . . . . . . . . . . . . .
6-9 Error Low Address Register: 0x180000080 . . . . . . . . .
6-10 Error High Address Register: 0x1800000A0 . . . . . . . .
6-11 LDx_L Low Address Register: 0x1800000C0 . . . . . . . .
6-12 LDx_L High Address Register: 0x1800000E0 . . . . . . .
Presence Detect Low-Data Register: 0x180000280 . . .
6-13
6-14 Presence Detect High-Data Register: 0x180000260 . . .
Bank 0 Base Address Register: 0x180000800 . . . . . . .
6-15
6-16 Configuration Registers for Bank Set 0:
0x180000A00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-17 Bank Set 0 Timing Register A: 0x180000C00 . . . . . . . .
6-18 Bank Set 0 Timing Register B: 0x180000E00 . . . . . . . .
6-19 Global Timing Register: 0x180000200 . . . . . . . . . . . . .
2-26
2-27
3-2
4-15
4-23
4-30
4-31
4-32
5-2
5-6
5-12
5-17
5-19
5-21
6-1
6-2
6-3
6-5
6-6
6-11
6-14
6-16
6-19
6-19
6-20
6-20
6-21
6-21
6-22
6-22
6-25
6-26
6-28
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