Sio Chip Pci Configuration Space; Pci Control Register - DEC Digital Alpha VME 4/224 User Manual

• NVRAM
• Interval timers
The bottom 1 MB in PCI sparse memory space is mapped onto the Nbus for use
by the flash ROM.
These address regions are negatively decoded and are not affected by any other
PCI device that is programmed to positively decode PCI addresses.
The CPU can access the Nbus devices in I/O space on a byte-by-byte basis.
Digital Alpha VME 4 only supports single-byte accesses to all Nbus locations.
Most resources of the Nbus are accessed as the least-significant byte of aligned
longwords. The exceptions are the time-of-year (TOY) clock and the ROM. Both
of these regions are contiguous bytes. When accessing the Nbus, only one PCI
byte enable is asserted.
9.1.1 SIO Chip PCI Configuration Space
CPU Address: 0x1E0030000 - 0x1E0031FE0
PCI Configuration: 0x00004000 - 0x000040FF
The SIO chip does not have any base address registers. Instead, the SIO
chip negatively decodes fixed regions in both PCI I/O and PCI memory space.
However, the following registers are used in PCI bus and Nbus control:
•

PCI control register

• ISA controller recovery timer register
• ISA clock divisor register
Figure 9–2 shows the layout of the SIO chip configuration space with these
registers. For more detail, see Intel's SIO82378 Chip Specification.
9–2 Nbus