Decchip 21071-Da Csr Space (0X1A0000000 To 0X1Afffffff); Pci Interrupt Acknowledge/Special Cycle Space (0X1B0000000 To 0X1Bfffffff); Pci Sparse I/O Space (0X1C0000000 To 0X1Dfffffff) - DEC Digital Alpha VME 4/224 User Manual

5.1.4 DECchip 21071-DA CSR Space (0x1A0000000 to
0x1AFFFFFFF)
The DECchip 21071-DA responds to all accesses in this space. Section 7.4
specifies the registers and associated register addresses. Section 7.5 contains the
register descriptions.
5.1.5 PCI Interrupt Acknowledge/Special Cycle Space
(0x1B0000000 to 0x1BFFFFFFF)
A read access to this space causes an interrupt acknowledge cycle on the PCI.
Bits sysBus<6:3> are used to generate the byte enables on the PCI as specified
in Table 5–2. Bits sysBus<26:7> are in a don't care state during this transaction.
A write access to this space causes a special cycle on the PCI. The address and
byte enables are in a don't care state during this transaction.
Software must use an STL instruction to initiate these transactions.

5.1.6 PCI Sparse I/O Space (0x1C0000000 to 0x1DFFFFFFF)

The PCI sparse I/O space is a 512 MB system bus address space that maps to 16
MB of PCI I/O address space. A read or write transaction to this space causes a
PCI I/O read or PCI I/O write command respectively.
Bits sysBus<33:29> identify the various address spaces on the system bus.
Bits sysBus<6:3> generate the length of the PCI transaction in bytes, the byte
enables, and ad<2:0> on the PCI bus (see Table 5–2).
Bits sysBus<28:8> correspond to the quadword PCI addresses and are sent out
on ad<23:3> during the address phase on the PCI. Bits ad<31:24> are obtained
from one of two host address extension registers (HAXR0 and HAXR2). The
HAXR0 register (which is hardcoded as 0) is used for system bus addresses
between 0x1C0000000 and 0x1C07FFFFF (that is, when bits sysBus<28:23> are
0).
The HAXR2 register maps system bus addresses between 0x1C0800000 and
0x1DFFFFFFF (that is, when bits sysBus<28:23> are nonzero anywhere in the
PCI address space). The HAXR2 register is a CSR in the 21071-DA chip and
is fully programmable. This allows Nbus devices that require their I/O space
to be in the lower 256 KB to coexist with other devices that do not have that
restriction. The lower 256 KB of I/O space have fixed mapping (HAXR0 to 0), and
the remaining I/O space (64 MB minus 64 KB) can be programmed anywhere in
PCI space.
Note
System Address Mapping 5–5