Interrupt And Interrupt Mask Registers 1, 2, 3, 4; Memory Configuration Registers 0, 1, 2, 3 And Memory Identification Register - DEC Digital Alpha VME 4/224 User Manual

Table 9–2 (Cont.) Module Configuration Register
Field Name Type
<6:5> CPU ID RO

9.2.3 Interrupt and Interrupt Mask Registers 1, 2, 3, 4

See Chapter 11 for descriptions of these registers.
9.2.4 Memory Configuration Registers 0, 1, 2, 3 and Memory
Identification Register
• Memory configuration 0
CPU address: 0x1C00100C0
Nbus offset: 0x806
• Memory configuration 1
CPU address: 0x1C00100E0
Nbus offset: 0x807
• Memory configuration 2
CPU address: 0x1C0010100
Nbus offset: 0x808
• Memory configuration 3
CPU address: 0x1C0010120
Nbus offset: 0x809
0x1C0010160
0x80B
The memory configuration and memory identification registers store the presence
detect (PD) bits and the ID bits of the main memory DIMMs as shown in Figures
9–6 and 9–7.
9–8 Nbus
Description
Determine the speed of the CPU according to the following
table:
<6:5> Definition
00 224 MHz
01 288 MHz
10 Reserved
11 Reserved