Error Low Address Register; Maximum Memory Tag Enable Values - DEC Digital Alpha VME 4/224 User Manual

Table 6–5 Maximum Memory Tag Enable Values
TAGEN<15:0>
1
1111 1111 1111 1110
0111 1111 1111 1110
0011 1111 1111 1110
0001 1111 1111 1110
0000 1111 1111 1110
0000 0111 1111 1110
0000 0011 1111 1110
0000 0001 1111 1110
0000 0000 1111 1110
0000 0000 0111 1110
0000 0000 0011 1110
0000 0000 0000 1110
0000 0000 0000 0110
0000 0000 0000 0010
0000 0000 0000 0000
1
TAGEN<0> is reserved and must be zero.

6.6.4 Error Low Address Register

When an error sets the BC_TAPERR, BC_TCPERR, or NXMERR bit in the
error and diagnostic status register, the error low address register latches the
low-order bits of the sysadr<20:5> address that caused the error. If a victim read
caused the error, the victim address is not latched. Instead, the address of the
transaction is latched.
The register is shown in Figure 6–9. Bits <15:0> represent sysadr<20:5>. This
register is read-only. It is not initialized and is valid only when an error is
indicated.
6–18 Cache and Memory Subsystem
Compared
Bits Memory Size
<31:17> 4 GB
<30:17> 2 GB
<29:17> 1 GB
<28:17> 512 MB
<27:17> 256 MB
<26:17> 128 MB
<25:17> 64 MB
<24:17> 32 MB
<23:17> 16 MB
<22:17> 8 MB
<21:17> 4 MB
<19:17> 1 MB
<18:17> 512 KB
<17> 256 KB
None 128 KB