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6.3.7 Presence Detect Logic
The DECchip 21071-CA supports loading the status of 32 presence detect bits
from the memory configuration registers 0 to 3 and the memory identification
register after reset.
6.4 Error Handling
During CPU and DMA transactions, the DECchip 21071-CA detects the following
errors:
•
Bcache tag address parity error
•
Bcache tag control parity error
•
Nonexistent memory error
When an error is detected, the DECchip 21071-CA acknowledges a hard
error condition on the cack<2:0> or iocack<1:0> signal lines at the end of
the transaction to signal the error to the CPU or the 21071-DA. The current
sysadr<33:5> is logged in the error address register, and the error status is
logged in the error and diagnostic status register. These CSRs are locked until
the CPU clears all the error status bits by writing to the error register.
If errors occur on a transaction while the error address and status are locked, the
following occurs:
•
The transaction is acknowledged with a hard error condition on the
cack<2:0> or iocack<1:0> fields.
•
The LOSTERR bit in the error and diagnostics status register is set.
•
The lost error address and status are not recorded.
The hard error condition overrides STx_C transaction fail. The lock bit is
UNPREDICTABLE after LDx_L transactions complete with errors.
6.5 Address Space of Control/Status Registers
CPU address: 0x180000000 - 0x19FFFFFFF
This section describes the control/status registers (CSRs) of the
DECchip 21071-CA. The DECchip 21071-CA responds to all CSR accesses in this
space.
The CSRs are 16 bits wide and are addressed on cache-line boundaries. Write
transactions to read-only registers could result in UNPREDICTABLE behavior;
read transactions are nondestructive. Only bits <15:0> of each register are
defined. Zeros must be written to unspecified bits within a CSR. CSRs are
initialized as shown in the Type column of the register tables.
6–8 Cache and Memory Subsystem
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