Timer Modes - DEC Digital Alpha VME 4/224 User Manual

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interrupt request (IRQ). The IRQ can be dismissed by an access to the timer
interrupt status register.

9.7.3 Timer Modes

Of the six timer modes of which the 82C54 chip is capable, Digital Alpha VME 4
implements the following counting modes:
Table 9–17 Timer Modes
Mode
Description
0
Software retriggerable one-shot timer
1
Hardware retriggerable one-shot timer
3
Periodic square wave generator
5
Hardware triggered strobe
Timer #0 Does Not Support Modes 1 and 5
Timer #0 does not function properly in modes 1 and 5. These modes are needed
to support the distributed timer functionality across the VME backplane. The
circuitry supporting timer #0 will be changing to enable modes 1 and 5. When
this change occurs, all modes other than 1 and 5, will be disabled. As a result,
this timer should not be used until this problem has been corrected.
For timers #0 and #2, which can cause timer interrupts through the interrupt
register 3<3> (reported through the timer interrupt status register), an output
low-to-high transition is considered to be the timer expiration that causes a status
bit to be set and, if enabled, the interrupt request to be asserted.
Timer #1 can cause an interrupt through the VIC64 chip local IRQ3 only. Even
though the VIC64 chip can be programmed to accept either assertion level at its
local IRQ input, it is usually configured to generate an interrupt on the rising
edge of timer #1 output.
Mode 0 - Software Retriggerable One-Shot
This mode allows a value to be written to the timer, which then counts down,
asserting the output (high) when it reaches 0. In this mode, it takes N+1
clock ticks from the end of the counter value write cycle until the output
makes an active transition.
If a new count value is written during the counting sequence, it is loaded on
the next clock pulse and counting continues from the new value. This means
the count is software retriggerable.
Restrictions
Timers

N
3
1, 2
N>=2, CLK<3 MHz
0 only
N>=5
1, 2
CLK<3 MHz
0 only
Nbus 9–29

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