Watchdog Timer Interrupt Test - DEC Digital Alpha VME 4/224 User Manual

Watchdog Timer Interrupt Test

This test verifies the functionality of the watchdog timeout by its ability to handle
a user programmed watchdog reset.
This test checks the following logic:
• Watchdog timer
• Some reset logic
• DS1386 TOY clock
Watchdog Timer Interrupt Test
The diagnostic-in-progress bit is set and a watchdog timeout is invoked by loading
a short time value into the watchdog timeout register. The user is queried to be
sure the watchdog LED is off. Upon expiration of the watchdog, a HALT interrupt
is expected. After the expected time, the reset reason register is evaluated. If
the HALT interrupt did not occur, or the watchdog reason was not set, an error
callout is made. Also, the user is asked to verify the watchdog LED is now on.
At the end of the test, the watchdog timer and diagnostic-in-progress bit are
disabled.
Console Command: wdog_diag -t 1
Command Options:
• -dd: print detailed test information on each pass.
• -nc: no confirmation; user is not prompted to verify state of LED
• -np: no print; overrides the -nc option, no user prompts
Miscellaneous Note
The purpose of setting the diagnostic-in-progress bit is to avoid an actual system
reset when the watchdog timer expires. The watchdog expiration first causes
a HALT interrupt. Approximately 300 ms later an actual system reset occurs,
unless the diagnostic-in-progress bit is set. The reset reason register shows
a watchdog reset reason whether or not the diagnostic-in-progress bit is set.
The HALT interrupt and the reset reason are used for this diagnostic. User
interaction can be suppressed with the -nc option (no confirmation).
Watchdog Timer Interrupt Test
Diagnostics 4–27