Data Coherency - DEC Digital Alpha VME 4/224 User Manual

7.3.3 Data Coherency

The two agents that must synchronize their data transfers are the CPU and any
PCI device. The PCI host bridge maintains data coherency and synchronization
between the agents using the following mechanisms:
• Maintains strict ordering of DMA write transactions initiated on the PCI bus.
• Allows DMA read transactions to bypass write transactions that are not to
the same address (double cache line) but maintains strict ordering between
read and write transactions to the same address.
• Performs I/O transfers from the CPU to the PCI host bridge in order. This
policy guarantees a coherent view of PCI I/O space from the CPU.
• Flushes DMA write data to memory before acknowledging a memory barrier
command from the CPU. The memory barrier command is used to order CPU
and DMA accesses because explicit ordering commands are absent on the PCI
bus.
• Flushes the I/O write buffer to the PCI bus before acknowledging a memory
barrier command. This policy maintains the order between CPU I/O accesses
and CPU memory accesses.
• Clears the system lock flag on read and write transactions to system memory
that are exclusive to the PCI bus.
Some data transfers require both the system bus and the PCI bus to complete.
For example, CPU I/O transfers require ownership of the system bus followed by
ownership of the PCI bus. In the same way, PCI bus masters' DMA transactions
with the memory subsystem require ownership of the PCI followed by ownership
of the system bus.
During read transfers (I/O or DMA), both buses must be held at the same time
for the transfer to complete. During write transfers (I/O or DMA), only one bus
must be held because the PCI host bridge features write-and-run style buffering.
However, when a write buffer is full, both buses must be held at the same time so
that some data from the write buffer can be flushed before new data is accepted.
The PCI host bridge resolves the deadlock by forcing the CPU to give up
ownership of the system bus, using a preemption request. Once the system
bus is released, the PCI host bridge gives priority to a PCI device for use of the
system bus.
The PCI host bridge provides the system designer flexibility in the choice of
PCI devices, that is, it supports devices that use the PCI disconnect in handling
deadlock situations.
PCI Host Bridge 7–5