DEC Digital Alpha VME 4/224 User Manual page 433

Interval timing registers, 9–25
ioclrlock command, 7–6
iogrant signal, 7–6
ISA
bus controller recovery timer register,
9–4
clock divisor register, 9–4
J
Jumpers
cache, settings of, 2–13
SCSI termination, 2–16
setting watchdog signal, 2–16
K
Keyboard
cables, connecting, 2–21
connector pinouts, A–7
controller, 9–21
Keys, console command, 13–1
kill command, 13–61
Kit contents, 2–1
L
LAN address ROM test, 4–22
LAN address ROM verification test, 4–22
LANGUAGE environment variable, 3–6
LANGUAGE_NAME environment
variable, 3–6
Latency, memory read, 6–7
Layout
Digital Alpha VME 4 (figure), 2–7
I/O modules (figure), 2–8
LDx_L high address register, 6–20
LDx_L low address register, 6–19
LICENSE environment variable, 3–6
line command, 13–62
Longword swap mode, 10–26
ls command, 13–63
M
Master DMA transfer, 10–9
memexer command, 13–64
Memory, 1–2, 6–1
accessing data in, 12–9
address of, 6–1
bits, testing, 4–7
cache, 2–12
configuration registers of, 9–8
configurations, 2–11
control registers of, 6–20
data paths of, 6–1
depositing data in, 12–7
diagnostic test, 4–7
diagnostic tests for, 4–3
DMA write buffer, 6–31
error handling for, 6–32
examining, 12–7
exerciser test, 4–3
generation of addresses for, 6–7
I/O and merge buffers, 6–31
I/O write and DMA read buffers, 6–31
identification register of, 9–8
installing main, 2–10
locking access to for PCI host bridge,
7–6
mapping pages from VMEbus to PCI
bus, 10–10
maximum tag enable values of, 6–18
modules required, 2–3
organization of, 6–6
read buffer for, 6–31
registers for, 9–8
write buffer, 6–32
Memory controller, 6–1, 6–5
error handling of, 6–8
memory timing of, 6–7
page mode support of, 6–7
presence detect logic of, 6–8
read latency, 6–7
transaction scheduler of, 6–7
Index–9