DEC Digital Alpha VME 4/224 User Manual page 432

G
General control register, 6–11
Global switches, 10–14
Global timing register, 6–27
grep command, 13–52
using pipe with, 12–12
H
Halt switch, 3–2
Hardware retriggerable one-shot mode (1),
9–30
Hardware triggered strobe mode (5),
9–30
HAXR0 register, 5–5
HAXR2 register, 5–5
hbeat_diag, 4–9
hd command, 13–55
Heartbeat
register, 9–14
timer test, 4–4, 4–9
help command, 13–57
Host address extension registers, 7–18
I
I/O
buffer, memory, 6–31
companion card
See PMC I/O companion card
module
configuration switches, setting,
2–9
redirecting, 12–12
subsystem, interface to, 8–1
Type 1 card connector pinouts, A–1
write buffer, memory, 6–31
i8254_diag command
with -t 1, 4–10
with -t 2, 4–11
with -t 3, 4–12
with -t 4, 4–13
with -t 5, 4–13
Index–8
i8254_diag command (cont'd)
with -t 6, 4–14
Identification (ID) bits, 9–11
Inbound scatter-gather entry, 10–12
Indicators, front panel
description, 3–2
figure, 3–1
initialize command, 13–60
init_ev command, 13–59
Installation, 2–6 to 2–27
of main memory, 2–10
of PMC I/O companion card, 2–23
of primary breakout module, 2–1,
2–15, 2–18
of secondary breakout module, 2–20
of system module, 2–14
Internet, booting hierarchy, 13–7
Interprocessor communication, 10–14
global switches, 10–14
module switches, 10–15
registers for, 10–14
Interrupt control register, general, 11–5
Interrupt delivery mechanism
testing, 4–9
Interrupt handling, for VMEbus, 10–23
Interrupt logic, 11–1
Interrupt mask registers, 9–8
Interrupt paths, testing, 4–28
Interrupt registers, 9–8
Interrupt/mask registers, 11–3
Interrupts
CPU, assignment of, 11–1
device, 11–6
EPIC, 11–13
PCI host bridge, 7–6
ranking of, 11–5
requesting, 11–7
sources of VIC64 chip, 11–6
status/error, 11–8
system, 11–1
Interval timer chip, testing, 4–10
Interval timer tests, 4–4, 4–10
Interval timing control register, 9–26