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Interrupts
4.4.1 Interrupt PLD Function
The MACH210A PLD is an 8-bit I/O slave on the ISA bus at hex addresses 804,
805, and 806. This is accomplished by a decode of the three ISA address bits
sa<2:0> and the three ecas_addr<2:0> bits.
Each interrupt can be individually masked by setting the appropriate bit in the mask
register (see Figure 4–6). An interrupt is disabled by writing a 1 to the desired posi-
tion in the mask register. An interrupt is enabled by writing a 0. For example, bit <1>
set in interrupt mask register 1 indicates that the INTB2 interrupt is disabled. There
are three mask registers located at ISA addresses 804, 805, and 806.
An I/O read transaction at ISA addresses 804, 805, and 806 returns the state of the 18
PCI interrupts rather than the state of the masked interrupts. On read transactions, a 1
means that the interrupt source has asserted its interrupt. The mask register can be
updated by writing addresses 804, 805, or 806. The mask register is write-only.
Figure 4–6 Interrupt/Interrupt Mask Registers
ISA Address 804
7
INTB0
ISA Address 805
7
INTD0
ISA Address 806
7
Reserved
Functional Description
4–14
6
5
IDE
SIO
Reserved
6
5
INTC3
INTC2
INTC1
6
5
Reserved Reserved Reserved
4
3
2
INTA3
INTA2
4
3
2
INTC0
INTB3
4
3
2
Reserved
INTD3
22 January 1998 – Subject To Change
1
0
INTA1
INTA0
1
0
INTB2
INTB1
1
0
INTD2
INTD1
MK2306-37
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