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This appendix describes the mapping of 21164 40-bit physical addresses to memory
and I/O space addresses. It also describes the translation of a 21164-initiated address
(addr_h<39:4>) into a PCI address (ad<63:0>) and the translation of a PCI-initiated
address into a physical memory address.
PCI addressing topics include dense and sparse address space and scatter-gather
address translation for DMA operations.
A.1 Address Map
The system address mapping operates with byte/word transactions enabled or dis-
abled. Byte/word operation is controlled by PYXIS_CTRL1<0> (IOA_BEN).
Table A–1 shows system address mapping operations when IOA_BEN equals 0
(byte/word operation disabled).
Table A–1 Physical Address Map (Byte/Word Mode Disabled)
21164 Address
00.000.0000 – 01.FFFF.FFFF
E.0000.0000 – E.FFFF.FFFF
80.0000.0000 – 83.FFFF.FFFF
84.0000.0000 – 84.FFFF.FFFF
85.0000.0000 – 85.7FFF.FFFF
85.8000.0000 – 85.BFFF.FFFF
85.C000.0000 – 85.FFFF.FFFF
86.0000.0000 – 86.FFFF.FFFF
87.0000.0000 – 87.1FFF.FFFF
22 January 1998 – Subject To Change
1
Size (GB)
16.00
System Address Space
Selection
8.00
Main memory
4.00
Dummy memory region
PCI sparse memory region 0, 512MB
4.00
PCI sparse memory region 1, 128MB
2.00
PCI sparse memory region 2, 64MB
1.00
PCI sparse I/O space region A, 32MB
1.00
PCI sparse I/O space region B, 32MB
4.00
PCI dense memory
0.50
PCI sparse configuration space
(Sheet 1 of 2)
System Address Space
A
A–1
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