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VMEchip2
Global Control and Status Registers
2
LCSR Programming Model
2-22
The VMEchip2 includes a set of registers that are accessible from
both the VMEbus and the local bus. These registers are provided to
aid in interprocessor communications over the VMEbus. These
registers are fully described in a later section.
This section defines the programming model for the Local Control
and Status Registers (LCSR) in the VMEchip2. The local bus map
decoder for the LCSR is included in the VMEchip2. The base
address of the LCSR is $FFF40000 and the registers are 32-bits wide.
Byte, two-byte, and four-byte read operations are permitted:
however, byte and two-byte write operations are not permitted.
Byte and two-byte write operations return a TEA signal to the local
bus. Read-modify-write operations should be used to modify a byte
or a two-byte of a register.
Each register definition includes a table with 5 lines:
Line 1 is the base address of the register and the number of
bits defined in the table.
Line 2 shows the bits defined by this table.
Line 3 defines the name of the register or the name of the bits
in the register.
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