852Gme/852Gmv/852Pmgmch/Ich4-M Platform Power-Up Sequence; Figure 97. Gmch / Ich4-M Platform Power-Up Sequence - Intel 852GME Design Manual

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12.4. 852GME/852GMV/852PMGMCH/ICH4-M Platform
Power-Up Sequence
Figure 97 describes the power-on timing sequence for a GMCH / ICH4-M-based platform.

Figure 97. GMCH / ICH4-M Platform Power-Up Sequence

Hub interface "CPU
Reset Complete"
message
STPCLK#,
CPUSLP#
Frequency
PCIRST#
SUS_STAT#
PWROK, VGATE
SLP_S3#
SLP_S4#
SLP_S5#
SUSCLK
RSMRST#,
RSM_PWROK
® ®
Intel 852GME, Intel 852GMV and Intel
System
G3 G3
State
Straps
T181
Vcc
T181
T173
VccSus
®
852PM Chipset Platforms Design Guide
Platform Power Delivery Guidelines
S5 S4 S3
T184
T185
T177
T176
T183b
T18 3a
T183
T182
S0 S0 state
T186
Strap Values
Normal Operation
T178
Running
211