Reset# Signal Termination - Intel Pentium III Processor 512K Design Manual

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LV Intel Pentium III Processor 512K Dual Processor Platform
Figure 9. RESET# Signal Termination
3.9.1.2 Signal Termination Requirements
Table 13 lists signal termination requirements for the debug port signals.
Table 13. Debug Port Termination Requirement
Signal
System Signal
POWERON
BCLK, BCLK#
BSEN#
DBRESET#
DBINST#
JTAG Signals
TCK
TDI
TDO
TMS
TRST#
Execution signals
RESET#
PREQx#
PRDYx#
22
V
TT
Rt
Load
RESET# Source
Signal Termination Value (Rt)
1.5 KΩ
240 Ω
240 Ω
10 KΩ
39 Ω
200 - 300 Ω
150 Ω
39 Ω
500 - 680 Ω
Match to AGTL characteristic
impedance
200 - 300 Ω
Match to AGTL characteristic
impedance
V
TT
Rt
Rs
Load
Termination
Value (Rs)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
240 Ω
N/A
240 Ω
Debug Port
Termination
Voltage (Rt)
V
TT
V
CC
V
CC
V
CC
GND
V CMOS
CC
V CMOS
CC
V CMOS
CC
GND
V
TT
V CMOS
CC
V
TT
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