Dual Channel Command Clock Routing; Dual Channel Command Clock Pair Routing Guidelines - Intel Xeon Design Manual

Intel
3.2.2

Dual Channel Command Clock Routing

Only one differential clock pair is routed to each DIMM connector because the MCH only supports
registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route
each clock and its compliment adjacent to each other. The two complimentary signals
(e.g., CMDCLK0 and CMDCLK0#) must be length matched to each other within ± 2 mils and
must be routed on the same layer. When a layer transition must occur, minimize the discontinuity in
the ground reference plane.
Table 9. Dual Channel Command Clock Pair Routing Guidelines
Parameter
Signal Group
Topology
Reference Plane
Differential Trace
Impedance (Zo)
Nominal Trace Width
Differential Trace
Spacing
Group Trace Spacing
MCH to DIMM1 Trace
Length
MCH to DIMM2 Trace
Length
MCH to DIMM3 Trace
Length
MCH to DIMM4 Trace
Length
MCH Breakout
Guidelines
Length Tuning
Requirements
NOTES:
1. Ensure angled DIMM connector pin length differences are accounted for when tuning lengths.
2. See the Intel
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
1-DIMM Solution
1, 1
0° 25° , 90°
100 Ω
± 10%
5 mils
7.5 mils
20 mils
3.0" to 4.0"
Not Supported
Not Supported
Not Supported
5/5, < 500 mils
CMDCLK to
CMDCLK#:
± 2 mils
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform
2-DIMM Solution
1
25°
CMDCLK[3:0], CMDCLK[3:0]#
Point to point
Ground
100 Ω ± 10%
5 mils
7.5 mils
20 mils
3.0" to 4.0"
4.0" to 6.0"
Not Supported
Not Supported
5/5, < 500 mils
CMDCLK to
CMDCLK#:
± 2 mils
®
E7500/E7501 Chipset Compatible Platform Design Guide.
2-DIMM Solution
Reference
90°
Figure 11
100 Ω ± 10%
Note 2
5 mils
7.5 mils
20 mils
3.0" to 4.0"
4.0" to 6.0"
Figure 11
Not Supported
Not Supported
5/5, < 500 mils
CMDCLK to
CMDCLK#:
Figure 11
± 2 mils
25