Clock Routing Topology For A Single Rank 4L Fly-By Design—Pcb Type 3 - Intel Quark SoC X1000 Design Manual

DDR3 Memory Design Guidelines—Intel
Table 10. Command Routing Guidelines and Settings for a Single Rank 4L Fly-by
Design—PCB Type 3 (Sheet 2 of 2)
Parameter
Trace Spacing (S1):
Between Command
Signals and the other
DDR groups
Trace Spacing (S2):
Between CMD group
and non-DDR signals -
excluding power pins
CMD group Trace
Segment Length
CMD group Total trace
length
Length matching
between CMD signals
and all the CLOCKs
within a Channel
(including pkg. length)
Number of vias
RTT Value
SoC BUffer Settings
CMD Timings
Note: All length matching and total trace length rules are applicable for the SoC to DRAM
paths; for Termination Segments (TL8 + TL9) only the min and max trace segment
length rules apply.
Figure 20. Clock Routing Topology for a Single Rank 4L Fly-by Design—PCB Type 3
SoC
Tx
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
min =
min =
13.0
4 mils
mils
min = min =
12 25.0
mils mils
min =
500
mils
max
= 300
max
mils
=
1700
mils
1st DRAM: TL1 + TL2 + TL3 +TL4 + TL10 = 3150 mils (max)
2nd DRAM: TL1 + TL2 + TL3 +TL4 + TL5 + TL6 + TL7 + TL10 = 3800 mils (max)
CMD = CLK/CLKB ± 150 mils
max = 4 via
36 Ω + 10%
RON: 27 Ω
SR: 1.5 V/ns
2N
Package
Breakout Main
P1
TL1 TL2
Cap
via
P1
TL1 TL2
Routing Guideline / Setting
min = min =
min = min =
6.5 6.5
4 mils 4 mils
mils mils
min = min = min = min =
25.0 12 12 25.0
mils mils mils mils
min =
min =
100
200
mils
max max
mils
= 100 = 100
max
mils mils
max
= 450
= 750
mils
mils
DRAM
Breakin
Breakin
Breakin
TL3 TL4 TL5 TL6
via
TL3 TL4
TL5 TL6
Breakout device-to- Breakin
-device
min =
min = min =
6.5
4 mils 4 mils
mils
min = min = min =
12 12 25.0
mils mils mils
min =
50
max max
mils
= 100 = 100
max
mils mils
= 600
mils
DRAM
Termination
RTT
TL7
via
TL7
Ctt
RTT
®
Intel Quark™ SoC X1000
min =
4 mils
min =
12
mils
min =
50
mils
max
= 300
mils
VTT
PDG
35