Data And Dqm Topology For Discrete Sdram Devices - Intel i960 Design Manual

Figure 4-9.

Data and DQM Topology for Discrete SDRAM Devices

8 0 9 6 0 R M / R N
I / O P r o c e s s o r
The address and control signals for the SDRAM subsystem include SA[11:0], SCAS#, SCE[1:0]#,
SCKE[1:0], SRAS#, and SWE#. The SDRAM data signals include DQ[63:0], and SCB[7:0].
Design Guide
S D Q [ 6 3 : 0 ] , S C B [ 7 : 0 ]
I n t e l®
R e s is t o r s m u s t b e w it h in 0 . 5
in c h e s f r o m th e S D R A M d e v ic e
Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor Memory Subsystem
D a t a s ig n a ls m u s t b e 3 t o 8
i n c h e s f r o m t h e p r o c e s s o r a n d
e a c h S D R A M d e v ic e
1 0 o h m s + / - 5 %
S D Q M [ 7 : 0 ]
1 0 o h m s + /- 5 %
*
S D R A M 0
S D Q M s i g n a l s m u s t b e 3 t o
9 . 5 in c h e s f r o m t h e p r o c e s s o r
a n d e a c h S D R A M d e v i c e
S D R A M 1
19