Single Channel Command Clock Routing; Single Channel 2-Dimm Command Clock Topology; Single Channel Command Clock Pair Routing Guidelines - Intel Xeon Design Manual

Processor and e7500/e7501 chipset compatible platform. addendum for embedded applications
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®
Intel
Xeon™ Processor and Intel
3.3.3

Single Channel Command Clock Routing

Only one differential clock pair is routed to each DIMM connector because the MCH only supports
registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route
each clock and its compliment adjacent to each other. The two complimentary signals
(e.g., CMDCLK0 and CMDCLK0#) must be length matched to each other within ± 2 mils and
must be routed on the same layer. When a layer transition must occur, minimize the discontinuity in
the ground reference plane.
Table 16. Single Channel Command Clock Pair Routing Guidelines
Parameter
Signal Group
Topology
Reference Plane
Differential Trace
Impedance (Zo)
Nominal Trace Width
Differential Trace Spacing
Group Trace Spacing
MCH to DIMM1 Trace
Length
MCH to DIMM2 Trace
Length
MCH Breakout Guidelines
Length Tuning
Requirements
NOTES:
1. Ensure angled DIMM connector pin length differences are accounted for when tuning lengths.
2. See the Intel
Figure 18. Single Channel 2-DIMM Command Clock Topology
NOTES:
1. CMDCLK/CMDCLK# must be matched to within ± 2 mils using package trace length compensation.
2. Unused CMDCLK/CMDCLK# pairs are no connects.
3. Indicated lengths measure from the MCH component pin to the DIMM connector pin.
36
®
E7500/E7501 Chipset Compatible Platform
1-DIMM Solution
1,
1,
25°
90°
2
100 Ω ± 10%
5 mils
7.5 mils
20 mils
3.0" to 4.0"
Not Supported
5/5, < 500 mils
CMDCLK to
CMDCLK#:
± 2 mils
®
Xeon™ Processor and Intel
CMDCLK0 & CMDCLK0#
Channel A
CMDCLK1 & CMDCLK1#
MCH
2-DIMM Solution
1
1
25°
CMDCLK[3:0], CMDCLK[3:0]#
Point to point
Ground
100 Ω ± 10%
5 mils
7.5 mils
20 mils
3.0" to 4.0"
4.0" to 6.0"
5/5, < 500 mils
CMDCLK to
CMDCLK#:
± 2 mils
®
E7500/E7501 Chipset Compatible Platform Design Guide.
DIMMs
Platform Design Guide Addendum
2-DIMM Solution
Reference
90°
Figure 18
100 Ω ± 10%
Figure 20
5 mils
7.5 mils
20 mils
3.0" to 4.0"
Figure 18
4.0" to 6.0"
5/5, < 500 mils
CMDCLK to
CMDCLK#:
Figure 18
± 2 mils

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