Serial Peripheral Interface (Spi) Topology Guidelines; Spi Single Flash Device Topology Guidelines; Spi Single Flash Device Routing Guideline; Legacy Spi Topology (Single Device) - Intel Quark SoC X1000 Design Manual

11.3

Serial Peripheral Interface (SPI) Topology Guidelines

This section contains preliminary information and details for layout and routing
guidelines for Intel
directly connected to the Intel
refer to the Serial Flash vendor documentation for additional Serial Flash specific design
considerations.
11.3.1

SPI Single Flash Device Topology Guidelines

Figure 39.

Legacy SPI Topology (Single Device)

11.3.1.1

SPI Single Flash Device Routing Guideline

Figure 40. SPI Single Flash Device Routing Guidelines for LSPI0_MOSI, LSPI0_MISO,
LSPI0_CS_N,LSPI0_SCK
Table 44. LSPI0_MOSI, LSPI0_MISO, LSPI_SS_B, LSPI0_SCK (Sheet 1 of 2)
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Single-
ended)
Trace Width (w)
Trace Spacing(S2): Between GPIO
Signals
®
Intel Quark™ SoC X1000
PDG
82
®
Quark™ SoC X1000 SPI interface. The Legacy SPI flash must be
®
S o C
L S P I _ M O S I
L S P I _ M IS O
L S P I_ C L K
L S P I_ S S _ B
SoC
Breakout
L
A
®
Intel Quark™ SoC X1000—SPI Flash Design Guidelines
Quark™ SoC X1000 Legacy SPI bus in all SKUs. Also,
Rs
L L
B C
Breakout
4 Layer 4 Layer
L L
A B
MS MS
4.2 mil 4.2 mil
4.2 mil 10 mil
S e ria l F la s h
S e ria l In p u t
S e ria l O u tp u t
C lo c k
C h ip S e le c t
Legacy SPI
L
Flash
D
Device
4 Layer 4 Layer
L
C
MS
50 Ω +/- 10%
4.2 mil 4.2 mil
10 mil 4.2 mil
Order Number: 330258-002US
L
D
MS
June 2014