Agilent Technologies HP 8719D Service Manual page 272

communicate with each other through DRAM. This also verifies that
programs can be loaded to the DSP, and that most of the main RAM
access circuits operate correctly.
DSP RAM. Verifies
6
processor by using a write/read pattern.
DSP ALU. Verifies
7
the digital signal processor.
DSP Intrpt.
8
respond to interrupts from the A10 digital IF ADC.
DIF Control.
9
write/read to the control latches on the A10 digital IF.
DIF Counter.
10
write/read to the triple divider on the A10 CPU. It tests the A7
CPU data buffers and A10 digital IF, the 4 MHz clock from the Al2
reference.
DSP Control.
11
write to the control latches on the A10 digital IF Feedback is verified
by the main processor. It primarily tests the A10 digital IF, but failures
may be caused by the A7 CPU.
12
write/read to the front panel processor. It tests the A2 front panel
interface and processorand A7 CPU data buffering and address
decoding. (See also tests 23 and 24 below.) This runs only when
selected.
Panel.
13
write/read to the rear panel control elements It tests the Al6 rear
panel, and A7 CPU data buffering and address decoding. (It does not
test the HP-IB interface; for that see the HP-IB Programming Guide.)
This runs only when selected or with ALL INTERNAL.
Post
14 Reg. Polls the status register of the A8 post-regulator, and
flags these conditions: heat sink too hot, inadequate air flow, or
post-regulated supply shutdown.
the A7 CPU RAM associated with the digital signal
the A7 CPU high-speed math processing portions of
Tests the ability of the A7 CPU digital signal processor to
Tests the ability of the A7 CPU main processor to
Tests the ability of the A7 CPU main processor to
Tests the ability of the A7 CPU digital signal processor to
Tests the ability of the A7 CPU main processor to
Tests the ability of the A7 CPU main processor to
Service Key Menus and Error Messages
1 O-13