General Control-Status/Feature Registers - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

General Control-Status/Feature Registers

2
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
2-70
The General Control-Status Register (GCSR) provides miscellaneous
control and status information for the PHB. The bits within the GCSR are
defined as follows:
1
0
GCSR
LEND Endian Select. If set, the PPC bus is operating in little
endian mode. The PPC address will be modified as
described in the section titled
Little Endian on page
bus is operating in Big Endian mode, and all data to/from
PCI is swapped as described in the section titled
PPC Devices are Big-Endian on page
PFBR PCI Flush Before Read. If set, the PHB will guarantee
that all PPC initiated posted write transactions will be
completed before any PCI initiated read transactions will
be allowed to complete. When PFBR is clear, there will be
no correlation between these transaction types and their
order of completion. Please refer to the section on
Transaction Ordering for more information.
XMBH PPC Master Bus Hog. If set, the PPC master of the PHB
will operate in the Bus Hog mode. Bus Hog mode means
the PPC master will continually request the PPC bus for
the entire duration of each transfer.
If Bus Hog is not enabled, the PPC master will request the
bus in a normal manner. Please refer to the section titled
PPC Master
$FEFF0008
1 1 1 1 1 1 1 1 1
1 2 3 4 5 6 7 8 9
2-39. When LEND is clear, the PPC
for more information.
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2 2 2 2 2 2 2 2 2
0 1 2 3 4 5 6 7 8
When PPC Devices are
When
2-38.
2 3 3
9 0 1