Xilinx RocketIO User Manual page 40

R
Table 2-1: Clock Ports
Table 2-2: Reference Clock Usage
40
±100 ppm or better, with jitter as low as possible. Module 3 of the Virtex-II Pro data sheet gives
further details.
Clock I/Os
BREFCLK Input
BREFCLK2 Input
RXRECCLK Output
REFCLK Input
REFCLK2 Input
REFCLKSEL Input
RXUSRCLK Input
(1)
TXUSRCLK Input
RXUSRCLK2 Input
(1)
TXUSRCLK2 Input
Notes:
1. TXUSRCLK and TXUSRCLK2 must be driven by clock sources, even if only the receiver of the MGT is being
used.
600 Mb/s –
2.499 Gb/s
√
REFCLK
√
BREFCLK
Notes:
1. Because of dedicated routing to reduce jitter, BREFCLK cannot be routed through the fabric.
Chapter 2: Digital Design Considerations
Reference clock used to read the TX FIFO and multiplied by 20 for
parallel-to-serial conversion (20X)
Alternative to BREFCLK
Recovered clock (from serial data stream) divided by 20. Clocks
data into the elastic buffer.
Reference clock used to read the TX FIFO and multiplied by 20 for
parallel-to-serial conversion (20X)
Alternative to REFCLK.
Selects which reference clock is used. 0 selects REFCLK; 1 selects
REFCLK2.
Clock from FPGA used for reading the RX Elastic Buffer. Clock
signals CHBONDI and CHBONDO into and out of the transceiver.
This clock is typically the same as TXUSRCLK.
Clock from FPGA used for writing the TX Buffer. This clock must
be frequency locked to REFCLK for proper operation.
Clock from FPGA used to clock RX data and status between the
transceiver and FPGA fabric. The relationship between
RXUSRCLK2 and RXUSRCLK depends on the width of the
receiver data path. RXUSRCLK2 is typically the same as
TXUSRCLK2.
Clock from FPGA used to clock TX data and status between the
transceiver and FPGA fabric. The relationship between
TXUSRCLK2 and TXUSRCLK depends on the width of the
transmission data path.
Data Rate
2.500 Gb/s –
3.125 Gb/s
√
www.xilinx.com
1-800-255-7778
Description
Routing
Can Route Can Route
Across Chip? Through BUFG?
√
Note (1)
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
√
Note (1)