Xilinx RocketIO User Manual page 49

Clocking
Verilog Template
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
PSDONE : out std_logic;
STATUS : out std_logic_vector ( 7 downto 0 )
);
end component;
--
-- Signal Declarations:
--
signal GND : std_logic;
signal CLK0_W : std_logic;
signal CLKDV_W : std_logic;
signal USRCLK2_M_W: std_logic;
begin
USRCLK2_M <= USRCLK2_M_W;
GND <= '0';
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN =>
CLKFB =>
DSSEN =>
PSINCDEC =>
PSEN =>
PSCLK =>
RST =>
CLK0 =>
CLKDV =>
LOCKED =>
);
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M
);
U3_BUFG: BUFG
port map (
I => CLKDV_W,
O => USRCLK2_M_W
);
end FOUR_BYTE_CLK_arch;
// Module: FOUR_BYTE_CLK
// Description: Verilog Submodule
// DCM for 4-byte GT
//
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REFCLK,
USRCLK2_M_W,
GND,
GND,
GND,
GND,
RST,
CLK0_W,
CLKDV_W,
LOCK
R
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