Clock Pulse Width; Timing Parameter Tables And Diagram - Xilinx RocketIO User Manual

R

Clock Pulse Width

ParameterName Format:
Pulse Width (Examples):

Timing Parameter Tables and Diagram

The following four tables list the timing parameters as reported by the implementation tools relative
to the clocks given in
clock. (No signals are synchronous to REFCLK or TXUSRCLK.)
A timing diagram
•
•
•
•
Table A-2: Parameters Relative to the RX User Clock (RXUSRCLK)
Parameter
Setup/Hold:
T _CHBI/T _CHBI
GCCK GCKC
Clock to Out:
T _CHBO
GCKCO
Clock:
T
RXPWH
T
RXPWL
128
T = Minimum pulse width, High state
xPWH
T = Minimum pulse width, Low state
xPWL
where
x = REF (REFCLK)
TX (TXUSRCLK)
TX2 (TXUSRCLK2)
RX (RXUSRCLK)
RX2 (RXUSRCLK2)
T Minimum pulse width, TX2 clock, Low state
TX2PWL
T Minimum pulse width, Reference clock, High state
REFPWH
Table A-1, along with the RocketIO signals that are synchronous to each
(Figure A-2) illustrates the timing relationships.
Table A-2, "Parameters Relative to the RX User Clock (RXUSRCLK)," page 128
Table A-3, "Parameters Relative to the RX User Clock2 (RXUSRCLK2)," page 129
Table A-4, "Parameters Relative to the TX User Clock2 (TXUSRCLK2)," page 129
Table A-5, "Miscellaneous Clock Parameters," page 130
Function
Control inputs
Control outputs
Clock pulse width, High state
Clock pulse width, Low state
www.xilinx.com
1-800-255-7778
Appendix A: RocketIO Transceiver Timing Model
CHBONDI[3:0]
CHBONDO[3:0]
RXUSRCLK
RXUSRCLK
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
Signals