Xilinx RocketIO User Manual page 60

R
Verilog Template
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end if;
end process;
end RTL;
// Module: gt_reset
// Description: Verilog Submodule
// reset for4-byte GT
//
// Device: Virtex-II Pro Family
module gt_reset(
USRCLK2_M,
DCM_LOCKED,
RST
);
input USRCLK2_M;
input DCM_LOCKED;
output RST;
wire USRCLK2_M;
wire DCM_LOCKED;
reg RST;
reg [7:0] startup_counter;
always @ ( posedge USRCLK2_M )
if ( !DCM_LOCKED )
startup_counter <= 8'h0;
else if ( startup_counter != 8'h02 )
startup_counter <= startup_counter + 1;
always @ ( posedge USRCLK2_M or negedge DCM_LOCKED )
if ( !DCM_LOCKED )
RST <= 1'b1;
else
RST <= ( startup_counter != 8'h02 );
endmodule
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Chapter 2: Digital Design Considerations
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004