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RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
The following table shows the revision history for this document.
Date
Version
11/20/01
1.0
01/23/02
1.1
02/25/02
1.2
07/11/02
1.3
09/27/02
1.4
10/16/02
1.5
11/20/02
1.6
12/12/02
1.6.1
03/25/03
2.0
UG024 (v2.3.2) June 24, 2004
• Initial Xilinx release.
• Updated for typographical and other errors found during review.
• Part of Virtex-II Pro™ Developer's Kit (March 2002 Release)
• Updated
"PCB Design
Requirements". Added
Model."
Changed Cell Models to Appendix B.
• Added additional IMPORTANT NOTE regarding ISE revisions at the beginning of Chapter 1
• Added material in section
• Added section
"Other Important Design Notes."
• New pre-emphasis eye diagrams in section
• Numerous parameter additions previously shown as "TBD" in
• Corrected pinouts for FF1152 package, device column 2VP20/30, LOC Constraints rows
GT_X0_Y0 and GT_X0_Y1.
• Corrected section
"CRC Latency"
and RXUSRCLK cycles.
• Corrected sequence of packet elements in
Table
1-2: Added support for XAUI Fibre Channel.
• Corrected max PCB drive distance to 40 inches.
• Reorganized content sequence in
Table
1-5: Additional information in RXCOMMADET definition.
• Code corrections in VHDL Clock templates.
"Data Path Latency"
section expanded and reformatted.
• Corrections in clocking scheme drawings. Addition of drawings showing clocking schemes
without using DCM.
Table
B-1: Corrections in Valid Data Characters.
Table
3-4: Data added.
• Corrections made to power regulator schematic,
Table
2-23: Data added/corrected.
• Added clarifying text regarding trace length vs. width.
• Reorganized existing content
• Added new content
• Added
Appendix C, "Related Online Documents"
• Added
"Index"
www.xilinx.com
1-800-255-7778
Revision
Appendix A, "RocketIO Transceiver Timing
"CRC (Cyclic Redundancy Check)."
"Pre-emphasis Techniques."
and
Table 2-20
to express latency in terms of TXUSRCLK
Figure
2-30.
Chapter 2, "Digital Design Considerations."
Figure
"MGT Package Pins."
3-7.
RocketIO™ Transceiver User Guide

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