Xilinx RocketIO User Manual page 46

R
Verilog Template
46
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M
);
end TWO_BYTE_CLK_arch;
//Module: TWO_BYTE_CLK
//Description: Verilog Submodule
// DCM for 2-byte GT
//
// Device: Virtex-II Pro Family
module TWO_BYTE_CLK (
REFCLKIN,
REFCLK,
USRCLK_M,
DCM_LOCKED
);
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output DCM_LOCKED;
wire REFCLKIN;
wire REFCLK;
wire USRCLK_M;
wire DCM_LOCKED;
wire REFCLKINBUF;
wire clk_i;
DCM dcm1 (
.CLKFB ( USRCLK_M ),
.CLKIN ( REFCLKINBUF ),
.DSSEN ( 1'b0 ),
.PSCLK ( 1'b0 ),
.PSEN ( 1'b0 ),
.PSINCDEC ( 1'b0 ),
.RST ( 1'b0 ),
.CLK0 ( clk_i ),
.CLK90 ( ),
.CLK180 ( ),
.CLK270 ( ),
.CLK2X ( ),
.CLK2X180 ( ),
.CLKDV ( ),
.CLKFX ( ),
.CLKFX180 ( ),
.LOCKED ( DCM_LOCKED ),
.PSDONE ( ),
.STATUS ( )
);
BUFG buf1 (
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Chapter 2: Digital Design Considerations
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004