Xilinx RocketIO User Manual page 50

R
50
// Device: Virtex-II Pro Family
module FOUR_BYTE_CLK(
REFCLKIN,
REFCLK,
USRCLK_M,
USRCLK2_M,
DCM_LOCKED
);
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output USRCLK2_M;
output DCM_LOCKED;
wire REFCLKIN;
wire REFCLK;
wire USRCLK_M;
wire USRCLK2_M;
wire DCM_LOCKED;
wire REFCLKINBUF;
wire clkdv2;
wire clk_i;
DCM dcm1 (
.CLKFB
.CLKIN
.DSSEN
.PSCLK
.PSEN
.PSINCDEC
.RST
.CLK0
.CLK90
.CLK180
.CLK270
.CLK2X
.CLK2X180
.CLKDV
.CLKFX
.CLKFX180
.LOCKED
.PSDONE
.STATUS
);
BUFG buf1 (
.I ( clkdv2 ),
.O ( USRCLK2_M )
);
BUFG buf2 (
.I ( clk_i ),
.O ( USRCLK_M )
);
IBUFG buf3(
.I ( REFCLKIN ),
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Chapter 2: Digital Design Considerations
( USRCLK_M ),
( REFCLKINBUF ) ,
( 1'b0 ),
( 1'b0 ),
( 1'b0 ),
( 1'b0 ),
( 1'b0 ),
( clk_i ),
( ),
( ),
( ),
( ),
( ),
( clkdv2 ),
( ),
( ),
( DCM_LOCKED ),
( ),
( )
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004