Index - Xilinx RocketIO User Manual

Index

Numerics
8B/10B Encoding/Decoding
67
bypassing
61
decoder
61
encoder
61
overview
ports and attributes 62
67
serial output format
133
8B/10B Valid Characters
A
114
AC and DC Coupling
Attributes & Ports (by function)
8B/10B encoding/decoding
89
buffers, fabric interface
81
channel bonding
74
clock correction
85
CRC
68
SERDES alignment
synchronization logic 77
Attributes (defined)
68
ALIGN_COMMA_MSB
CHAN_BOND__SEQ_LEN
82
CHAN_BOND_LIMIT
81
CHAN_BOND_MODE
CHAN_BOND_OFFSET
CHAN_BOND_ONE_SHOT
CHAN_BOND_SEQ_*_*
CHAN_BOND_SEQ_2_USE
82
CHAN_BOND_WAIT
CLK_COR_INSERT_IDLE_FLAG
CLK_COR_KEEP_IDLE
CLK_COR_REPEAT_WAIT
75
CLK_COR_SEQ_*_*
75
CLK_COR_SEQ_LEN
74
CLK_CORRECT_USE
71
COMMA_10B_MASK
CRC_END_OF_PACKET
85
CRC_FORMAT
CRC_START_OF_PACKET
DEC_MCOMMA_DETECT
DEC_PCOMMA_DETECT
DEC_VALID_COMMA_ONLY
MCOMMA_10B_VALUE
71
MCOMMA_DETECT
PCOMMA_10B_VALUE
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
PCOMMA_DETECT
PRE_EMPHASIS
RX_BUFFER_USE
RX_CRC_USE
RX_DATA_WIDTH
RX_DECODE_USE
RX_LOS_INVALID_INCR
RX_LOS_THRESHOLD
RX_LOSS_OF_SYNC_FSM
SERDES_10B
TERMINATION_IMP
TX_BUFFER_USE
TX_CRC_FORCE_VALUE
TX_CRC_USE
TX_DATA_WIDTH
62
TX_DIFF_CTRL
Attributes (table)
B
BREFCLK
and REF_CLK_V_SEL
and REFCLKSEL
and serial speed
81
pin numbers
when & how to use
Buffers, Fabric Interface
82
ports and attributes
81
transmitter and elastic (receiver)
81
Byte Mapping
81
C
75
75
Channel Bonding (Alignment)
75
operation
ports and attributes
troubleshooting
Vitesse channel bonding sequence
receive
88
transmit
Characters, valid (tables)
88
Clock Correction (Recovery)
71
clock recovery
71
overview
71
ports and attributes
71
Clock/Data Recovery (CDR) parameters
39
Clocking
71
clock and data recovery
71
91
74 90
,
85
90
62
77
77
77
90
90
89
88
85
90
91
28
31 41
,
25 41
,
39
41
41
89
89
89
37
79
80
81
83
66
65
133
73
72
74
106
72
www.xilinx.com
1-800-255-7778
clock correction (recovery)
57
clock dependency
125
clock descriptions
128
clock pulse width
43
clock ratio
clock recovery 73
39
clock signals
72
clock synthesizer
127
clock-to-output delays
code examples
51
1-byte clock
2-byte clock 44
47
4-byte clock
half-rate clocking scheme
multiplexed clocking scheme
56
with DCM
56
without DCM
Control Characters, valid (table)
114
Coupling, AC and DC
CRC (Cyclic Redundancy Check)
84
generation
84
latency
83
operation
85
ports and attributes
88
support limitations
D
133
Data Characters, valid (table)
57
Data Path Latency
68
Deserializer
Deterministic Jitter (DJ) 106
105
Differential Receiver
113
Differential Trace Design
H
55
Half-Rate Clocking Scheme
HDL Code Examples
Verilog
53
1-byte clock
46
2-byte clock
32-bit alignment design
49
4-byte clock
VHDL
1-byte clock 51
44
2-byte clock
32-bit alignment design
72
55
141
83
94
97
149