Xilinx RocketIO User Manual page 4

Date Version
06/12/03 2.1
11/07/03 2.2
RocketIO™ Transceiver User Guide
•
Table 1-2: Added qualifying footnote to XAUI 10GFC.
•
Table 1-5: Corrected definition of RXRECCLK.
• Section
"RocketIO Transceiver Instantiations" in Chapter
the Instantiation Wizard does.
•
Table 2-14: Changed numerics from exact values to rounded-off approximations (nearest
5,000), and added footnote calling attention to this.
• Section
"Clocking" in Chapter
clock input to FPGA fabric.
• Section
"RXRECCLK" in Chapter
divide-by-10. (RXRECCLK is always 1/20th the data rate.).
• Section
"CRC_FORMAT" in Chapter
"greater than 20".
•
Table 3-5: Clarified the significance of the V
• Section
"AC and DC Coupling" in Chapter
V /V settings when AC or DC coupling is used.
TRX TTX
•
Table 4-1: Corrected pinouts for FG256 and FG456.
•
Table 4-3: Corrected pinouts for FF1517 (XC2VP70).
• Section
"Clock Signals" in Chapter
♦ the reference clock must be provided at all times.
any added jitter on the reference clock will be reflected on the RX/TX I/O.
♦
•
Figure 2-3: Added a BUFG after the IBUFGDS reference clock buffer.
• Section
"RX_BUFFER_USE" in Chapter
"RXUSRCLK/RXUSRCLK2".
•
Table 2-20: Added footnotes qualifying the maximum receive-side latency parameters given
in the table.
• Section
"FIBRE_CHAN" in Chapter
bytes not including CRC placeholder).
• Section "ETHERNET" in Chapter
specifications must be adhered to.
•
Table 2-23: Corrected "External" to "Internal" loopback. Improved explanation of Parallel
Mode loopback.
• Added
Figure 2-28, "Serial and Parallel Loopback Logic."
• Section "Clock and Data Recovery" in Chapter
RXRECCLK is always 1/20th the incoming data rate, and that CDR requires a minimum
number of transitions to achieve and maintain a lock on the received data.
• Section
"Voltage Regulation" in Chapter
requirements when a device other than the LT1963 is used.
• Section
"AC and DC Coupling" in Chapter
V /V voltage compliance.
TRX TTX
•
Figure 3-17 and section
material specifying the optional use of an LVPECL buffer as an alternative to the LVDS buffer
previously specified.
•
Table 4-2: Added pinouts for FG676 package, XC2VP20 and XC2VP30.
•
Table A-5: Added BREFCLK parameters T
• Section
"Application Notes" in Appendix
XAPP648, XAPP669, and XAPP670.
• Various non-technical edits and corrections.
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Revision
2: added text recommending use of an IBUFGDS for reference
2: Deleted references to SERDES_10B attribute and to
2: Corrected minimum data length for USER_MODE to
/V
TTX TRX
3: Explanatory material added regarding
2: Added material that states:
2: Corrected erroneous "USRCLK2" to
2: Added specification for minimum data length (24
2: Added note indicating that Gigabit Ethernet 802.3 frame
3: Corrected text to make clear that
3: Added material defining voltage regulator
3: Added footnote to
"Epson EG-2121CA 2.5V (LVPECL Outputs)" in Chapter
BREFPWH
C: Included new Xilinx Application Notes
1: added text briefly explaining what
voltages shown in this table.
Table 3-7 clarifying
and T .
BREFPWL
UG024 (v2.3.2) June 24, 2004
3: Added