Xapp652: Word Alignment And Sonet/Sdh Deframing; And Differential Swing Control Attributes; Xapp661: Rocketio Transceiver Bit-Error Rate Tester; Xapp662: In-Circuit Partial Reconfiguration Of Rocketio Attributes - Xilinx RocketIO User Manual

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of a pseudo-random number generator, running at the same clock frequency. The same circuit is
used in the receiver to recover the original data transmitted. Obviously, the pseudo-random number
generators at each end of the link must be in phase. This is achieved using a known pattern of
framing information (which is actually transmitted unscrambled). This is covered in more detail in
XAPP652.

XAPP652: Word Alignment and SONET/SDH Deframing

This application note describes the logic to perform basic word alignment and deframing
specifically for SONET/SDH systems, where data is being processed at 16 bits or 64 bits per clock
cycle.
XAPP660: Partial Reconfiguration of RocketIO Pre-emphasis

and Differential Swing Control Attributes

This application note describes a pre-engineered solution for Virtex-II Pro devices using the IBM
PowerPC™ 405 core to perform a partial reconfiguration of the RocketIO™ multi-gigabit
transceivers (MGTs) pre-emphasis and differential swing control attributes. This solution is ideal for
applications where these attributes must be modified to optimize the MGT signal transmission for
various system environments while leaving the rest of the FPGA design unchanged. The hardware
and software elements of this solution can be easily integrated into any Virtex-II Pro design. The
associated reference design supports the following devices: XC2VP4, XC2VP7, XC2VP20, and
XC2VP50. The design discussed in this document uses the PPC405 core device control register
(DCR) bus interface to implement a simple solution with a minimum of FPGA resources.

XAPP661: RocketIO Transceiver Bit-Error Rate Tester

This application note describes the implementation of a RocketIO transceiver bit-error rate tester
(BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s) between two
RocketIO multi-gigabit transceivers (MGT) embedded in a single Virtex-II Pro FPGA. To build a
system, an IBM CoreConnect™ infrastructure connects the PowerPC™405 processor (PPC405) to
external memory and other peripherals using the processor local bus (PLB) and device control
register (DCR) buses. The reference design uses a two-channel Xilinx bit-error rate tester (XBERT)
module for generating and verifying high-speed serial data transmitted and received by the
RocketIO transceivers. The data to be transmitted is constructed using pseudorandom bit sequence
(PRBS) patterns. The receiver in XBERT module compares the incoming data with the expected
data to analyze for errors. The XBERT supports several different types of user selectable PRBS
patterns. Frame counters in the receiver are used to track the total number of data words (frames)
received, and total number of data words with bit errors. The processor reads the status and counter
values from the XBERT through the PLB Interface, then sends out the information to the UART.

XAPP662: In-Circuit Partial Reconfiguration of RocketIO Attributes

This application note describes in-circuit partial reconfiguration of RocketIO transceiver attributes
using the Virtex-II Pro internal configuration access port (ICAP). The solution uses a Virtex-II Pro
device with an IBM PowerPC™ 405 (PPC405) processor to perform a partial reconfiguration of the
RocketIO multi-gigabit transceivers (MGTs) pre-emphasis and differential swing control attributes.
These attributes must be modified to optimize the MGT signal transmission prior to and after a
system has been deployed in the field. This solution is also ideal for characterization, calibration,
and system testing.
The hardware and software elements of this solution can be easily integrated into any Virtex-II Pro
design already utilizing the PLB or OPB bus structures. The reference design uses a Xilinx
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Appendix C: Related Online Documents
www.xilinx.com
1-800-255-7778
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004