Xilinx RocketIO User Manual page 26

R
Table 1-5: GT_CUSTOM
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port
(3)
RXNOTINTABLE
(4)
RXP
RXPOLARITY
RXREALIGN
RXRECCLK
RXRESET
(3)
RXRUNDISP
RXUSRCLK
RXUSRCLK2
TXBUFERR
(3)
TXBYPASS8B10B
(3)
TXCHARDISPMODE
(3)
TXCHARDISPVAL
(3)
TXCHARISK
26
(1)
, GT_AURORA, GT_FIBRE_CHAN
Port
I/O
Size
O 1, 2, 4 Status of encoded data when the data is not a valid character when asserted
High. Applies to the byte-mapping scheme.
I 1 Serial differential port (FPGA external)
I 1 Similar to TXPOLARITY, but for RXN and RXP. When de-asserted, assumes
regular polarity. When asserted, reverses polarity.
O 1 Signal from the PMA denoting that the byte alignment with the serial data
stream changed due to a comma detection. Asserted High when alignment
occurs.
O 1 Clock recovered from the data stream by dividing its speed by 20.
I 1 Synchronous RX system reset that "recenters" the receive elastic buffer. It also
resets 8B/10B decoder, comma detect, channel bonding, clock correction logic,
and other internal receive registers. It does not reset the receiver PLL.
O 1, 2, 4 Signals the running disparity (0 = negative, 1 = positive) in the received serial
data. If 8B/10B encoding is bypassed, it remains as the second bit received (Bit
"b") of the 10-bit encoded data (see
I 1 Clock from a DCM or a BUFG that is used for reading the RX elastic buffer. It
also clocks CHBONDI and CHBONDO in and out of the transceiver.
Typically, the same as TXUSRCLK.
I 1 Clock output from a DCM that clocks the receiver data and status between the
transceiver and the FPGA core. Typically the same as TXUSRCLK2. The
relationship between RXUSRCLK and RXUSRCLK2 depends on the width of
RXDATA.
O 1 Provides status of the transmission FIFO. If asserted High, an
overflow/underflow has occurred. When this bit becomes set, it can only be
reset by asserting TXRESET.
I 1, 2, 4 This control signal determines whether the 8B/10B encoding is enabled or
bypassed. If the signal is asserted High, the encoding is bypassed. This creates
a 10-bit interface to the FPGA core. See the 8B/10B section for more details.
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what mode of disparity is
to be sent. When 8B/10B is bypassed, this becomes the first bit transmitted (Bit
"a") of the 10-bit encoded TXDATA bus section (see
each byte specified by the byte-mapping.
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what type of disparity is to
be sent. When 8B/10B is bypassed, this becomes the second bit transmitted
(Bit "b") of the 10-bit encoded TXDATA bus section (see
page 66) for each byte specified by the byte-mapping section.
I 1, 2, 4 If 8B/10B encoding is enabled, this control bus determines if the transmitted
data is a K-character or a Data character. A logic High indicates a K-character.
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Chapter 1: RocketIO Transceiver Overview
(2) (2)
, GT_ETHERNET ,
Definition
Figure 2-14, page
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
66).
Figure 2-13, page 66) for
Figure 2-13,