Xilinx RocketIO User Manual page 125

R
RocketIO Transceiver Timing Model
This appendix explains all of the timing parameters associated with the RocketIO™ transceiver
core. It is intended to be used in conjunction with Module 3 of the
Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to
the data sheet.
There are many signals entering and exiting the RocketIO core. (Refer to
presented in this section treats the RocketIO core as a "black box." Propagation delays internal to the
RocketIO core logic are ignored. Signals are characterized with setup and hold times for inputs, and
with clock to valid output times for outputs.
There are five clocks associated with the RocketIO core, but only three of these clocks—
RXUSRCLK, RXUSRCLK2, and TXUSRCLK2—have I/Os that are synchronous to them. The
following table gives a brief description of all of these clocks. For an in-depth discussion of clocking
the RocketIO core, refer to
Table A-1: RocketIO Clock Descriptions
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
Chapter 2, "Digital Design
CLOCK SIGNAL
REFCLK Main reference clock for RocketIO transceiver
TXUSRCLK Clock used for writing the TX buffer. Frequency-locked to REFCLK.
TXUSRCLK2 Clocks transmission data and status and reconfiguration data between
the transceiver and the FPGA core. Relationship between TXUSRCLK2
and TXUSRCLK depends on width of transmission data path.
RXUSRCLK Clock used for reading the RX elastic buffer. Clocks CHBONDI and
CHBONO into and out of the transceiver. Typically the same as
TXUSRCLK.
RXUSRCLK2 Clocks receiver data and status between the transceiver and the FPGA
core. Typically the same as TXUSRCLK2. Relationship between
RXUSRCLK2 and RXUSRCLK depends on width of receiver data path.
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Appendix A
Virtex-II Pro Data Sheet
Figure
Considerations.".
DESCRIPTION
and the
A-1.) The model
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